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PDF CLC949ACQ Data sheet ( Hoja de datos )

Número de pieza CLC949ACQ
Descripción Very Low-Power/ 12-Bit/ 20MSPS Monolithic A/D Convertter
Fabricantes National Semiconductor 
Logotipo National Semiconductor Logotipo



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August 1996
N
Comlinear CLC949
Very Low-Power, 12-Bit,
20MSPS Monolithic A/D Convertter
General Description
The Comlinear CLC949 is a 12-bit analog-to-digital converter sub-
system including 12-bit quantizer, sample-and-hold amplifier, and
internal reference. The CLC949 has been optimized for low power
operation with high dynamic range. The CLC949 has a unique
feature which allows the user to adjust internal bias levels in the
converter which results in a trade-off between power dissipation
and maximum conversion rate. With bias set for 220mW power
dissipation the converter operates at 20MSPS. Under these
conditions, dynamic performance with a 9.9MHz analog input is
typically 68dB SNR and 72dBc SFDR. When bias is set for only
65mW power dissipation the converter maintains excellent perfor-
mance at 5MSPS. With a 2.4MHz analog input signal the SNR is
70dB and SFDR is 78dBc. This excellent dynamic performance in
the frequency domain without high power requirements make the
part a strong performer for communications and radar applications.
The low input noise of the CLC949, its 0.5LSB differential linearity
error specification, fast settling, and low power dissipation also
lead to excellent performance in imaging systems. All parts are
thoroughly tested to insure that guaranteed specifications are met.
The CLC949 incorporates an input sample-and-hold amplifier
followed by a quantizer which uses a pipelined architecture to min-
imize comparator count and the associated power dissipation
penalty. An on-board voltage reference is provided. Analog input
signals, conversion clock, and a single supply are all that are
required for CLC949 operation.
Features
s Very low/programmable power
0.07W @ 5MSPS
0.22W @ 20MSPS
0.40W @ 30MSPS
s Single supply operation (+5V)
s 0.5 LSB differential linearity error
s Wide dynamic range
72dBc spurious-free dynamic range
68dB signal-to-noise ratio
s No missing codes
Applications
s CCD imaging
s IR imaging
s FLIR processing
s Medical imaging
s High definition video
s Instrumentation
s Radar processing
s Digital communications
The CLC949 exhibits very stable performance over the commercial
and industrial temperature ranges. Most parameters shift very
little as the ambient temperature changes from -40°C to 85°C. An
exception to this rule is the dynamic performance of the converter.
As the temperature is increased, the distortion increases,
especially at higher input frequencies. This can be seen in the plot
on page 3. For input frequencies below 7MHz, there is relatively
little variation in distortion as the temperature is changed, but at
higher input frequencies, it is apparent that the performance
degrades as the temperature is increased.
SFDR (dBc)
Note that the reason for this degradation is the reduced ability of
the CLC949 to handle high slew rates at high temperatures. In
applications such as CCD imaging systems, where the slew rate at
the A/D sampling instant is very low, this degradation will not be
nearly so pronounced.
For applications requiring high temperature operation and very low
distortion with high frequency input signals, use of an external
sample-and-hold amplifier may enhance performance by reducing
the slew rates that the CLC949 sees during its sampling period (just
after the falling edge of CLK).
The CLC949 is fabricated in a 0.9µm CMOS technology. The
CLC949ACQ is specified over the commercial temperature range
of 0°C to +70°C and the CLC949AJQ is specified over the indus-
trial range of -40°C to +85°C. Both are packaged in a 44-pin
Plastic Leaded Chip Carrier (PLCC).
© 1996 National Semiconductor Corporation
Printed in the U.S.A.
Power Dissipation vs. Conversion Rate
200
150
100
50
0
0 5 10 15 20
Sample Rate (MSPS)
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CLC949ACQ pdf
CLC949 OPERATION
Application
In a high speed data acquisition system, the overall
performance is often determined by the A/D converter
and its surrounding circuitry. You should pay special
attention to the data converter and its support circuitry if
you want to obtain the best possible performance. The
information on these pages is intended to help you
design the circuitry surrounding the CLC949 in such
a way as to achieve superior results. Additional
information is available in the form of Comlinear
applications notes. Especially useful are AD-01 and
AD-02.
Circuit Description
The CLC949 ADC consists of an input Sample-and-Hold
Amplifier (SHA) followed by a pipelined quantizer.
Internal reference sources and output data latches
complete the major functions required of an A/D
converter. Digital error correction in the quantizer helps
to provide accurate conversions of high speed dynamic
signals. The speed of the analog circuitry is determined
in part by the internal bias currents applied. The CLC949
allows you to make this important tradeoff between
power and performance through settings on two digital
control pins and for fine adjustments through the use of
an external resistor.
Timing and CLK Generation
The falling edge of the CLK pulse causes the input sam-
ple-and-hold amplifier to transition into the hold mode.
The sample is taken approximately 3ns after this falling
edge. The digitized data is presented to the output latch-
es 6 1/2 clock cycles later and is held until after the next
rising edge of CLK. This timing is shown in the timing
diagram, Figure 1.
Analog
Input
CLK
Output
Data
Effective Aperture Delay
Sample 0
Sample 2 Sample 4
Sample 1
Sample 3 Sample 5
Sample 7
Sample 6
Output Hold Time
Sample
-3 Valid
Sample
-2 Valid
Sample Sample
-1 Valid 0 Valid
Figure 1: Timing Diagram
The CLC949 is designed to operate with a CMOS clock
signal. To obtain the lowest possible noise when
digitizing a high frequency input, more care must be
taken in the generation of this clock than is usually
accorded to CMOS Clocks. To minimize aperture jitter
induced errors, the CLK needs to have as low a
jitter as possible and as fast an edge rate as possible. To
obtain a very low jitter clock from a sinusoidal source, the
circuit shown in Figure 2 is recommended.
Sinusoisal
Clock Input
0.1µF
+5V
50
1k
10k
1k
+5V +5V
2.2k 10k
9
+
3
8
CLC006
1 0.1µF
6
-
4
5
2.2k
50
10k
To CLC949
Clock
74AC04
0.1µF
Figure 2: Clock Generation
Here the CLC006 cable driver is used as a comparator to
generate a high speed clock. The CLC006 has less than
2ps of jitter and has rise and fall times less than 1ns. The
CLC006 output is then buffered by a 74AC04 which
maintains fast edge rates and provides CMOS levels for
the CLC949. If there is excessive jitter in the CLK, then
the digitized signal will exhibit an excessive amount of
noise, especially for high frequency inputs. For a more
detailed description of this phenomenon, please read the
Comlinear Application Note AD-03.
In addition to the circuitry generating the clock, the
layout of the clock distribution network can affect the
overall performance of the converter. To obtain the best
possible performance, a clock driver with very low output
impedance and fast edge rates such as the 74AC04,
should be placed as close as possible to the CLC949
clock input pin. Additional length in the circuit trace for
the clock will cause an increase in the jitter seen by the
converter. On the CLC949 evaluation board, the
E949PCASM, there is less than 1/16th of an inch
between the 74AC04 that is driving the clock input and
the input to the CLC949. If the system has several
CLC949s, and jitter is liable to generate problems, then
use a separate clock driver for each CLC949. Each
driver should be placed as close to the converter that it is
driving as is practicable.
Driving the Differential Input
The CLC949 has a differential input with a common
mode voltage of 2.25V. Since not all applications have a
signal preconditioned in this manner there is often a need
to do a single-ended-to-differential conversion and to add
offset. In systems which do not need to be DC coupled,
the best method for doing this is with an RF transformer
such as the Minicircuits TMO1-1T. This is an RF
transformer with a center tapped secondary which will
operate over a frequency range of 50kHz to 200MHz.
You can offset the input and split the phases simply by
connecting the center tap to the mid scale reference
output (VREFMO) as shown in Figure 3.
This set up can be realized on the CLC949 evaluation
board by enabling option 1. See E949PCASM data
sheet for details. A transformer coupled input will allow
the CLC949 to exhibit the best possible distortion
performance for high frequency input signals.
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