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PDF CLC5632 Data sheet ( Hoja de datos )

Número de pieza CLC5632
Descripción Dual/ High Output/ Programmable Gain Buffer
Fabricantes National Semiconductor 
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N
CLC5623
Triple, High Output, Video Amplifier
June 1999
General Description
The CLC5623 has a new output stage that delivers high output
drive current (130mA), but consumes minimal quiescent supply
current (3.0mA/ch) from a single 5V supply. Its current feedback
architecture, fabricated in an advanced complementary bipolar
process, maintains consistent performance over a wide range of
gains and signal levels, and has a linear-phase response up to
one half of the -3dB frequency.
The CLC5623 offers 0.1dB gain flatness to 15MHz and differen-
tial gain and phase errors of 0.06% and 0.06°. These features are
ideal for professional and consumer video applications.
The CLC5623 offers superior dynamic performance with a
148MHz small-signal bandwidth, 370V/µs slew rate and 4.4ns
rise/fall times (2Vstep). The combination of low quiescent power,
high output current drive, and high-speed performance make
the CLC5623 well suited for many battery-powered personal
communication/computing systems.
The ability to drive low-impedance, highly capacitive loads,
with minimum distortion, makes the CLC5623 ideal for cable
applications. The CLC5623 will drive a 100load with only
-78/-94dBc second/third harmonic distortion (Av = +2, Vout =
2Vpp, f = 1MHz). With a 25load, and the same conditions, it
produces only -82/-96dBc second/third harmonic distortion.
The CLC5623 can also be used for driving differential-input step-
up transformers for applications such as Asynchronous Digital
Subscriber Lines (ADSL) or High-Bit-Rate Digital Subscriber
Lines (HDSL).
When driving the input of high-resolution A/D converters, the
CLC5623 provides excellent -86/-96dBc second/third harmonic
distortion (Av = +2, Vout = 2Vpp, f = 1MHz, RL = 1k) and fast
settling time.
Features
s 130mA output current
s 0.06%, 0.06° differential gain, phase
s 3.0mA/ch supply current
s 148MHz bandwidth (Av = +2)
s -86/-96dBc HD2/HD3 (1MHz)
s 18ns settling to 0.05%
s 370V/µs slew rate
s Stable for capacitive loads up to 1000pf
s Single 5V or ±5V supplies
Applications
s Video line driver
s ADSL/HDSL driver
s Coaxial cable driver
s UTP differential line driver
s Transformer/coil driver
s High capacitive load driver
s Portable/battery-powered applications
s Differential A/D driver
Maximum Output Voltage vs. RL
10
9
8
7 VCC = ±5V
6
5
4
3 Vs = +5V
2
1
10 100
RL ()
1000
Typical Application
Single Supply Cable Driver
+5V
6.8µF
+
5k
Vin 0.1µF
5
4
+
0.1µF
1/3 7
10m of 75
75Coaxial Cable
Vo
5k
CLC5623
6-
11 1k
0.1µF
75
1k
0.1µF
Pinout
DIP & SOIC
NC 1
14 OUT2
NC 2
13 -IN2
NC 3
12 +IN2
+Vs 4
11 -Vs
+IN1 5
10 +IN3
-IN1 6 - + + - 9 -IN3
OUT1 7
8 OUT3
© 1999 National Semiconductor Corporation
Printed in the U.S.A.
http://www.national.com

1 page




CLC5632 pdf
±5V Typical Performance (Av = +2, Rf = 1k(PDIP), RL = 100, VCC = ±5V, unless specified)
Frequency Response
Vo = 1.5Vpp
PDIP Package
Gain
Av = +2
Rf = 750
Phase
Av = +1
Rf = 750
Av = +10
Rf = 200
Av = +5
Rf = 402
1M 10M 100M
Frequency (Hz)
0
-45
-90
-135
-180
-225
Frequency Response vs. Vo
PDIP Package
Vo = 0.1Vpp
Vo = 1Vpp
Vo = 5Vpp
Vo = 2Vpp
Inverting Frequency Response
Vo = 1.5Vpp
PDIP Package
Av = -5
Rf = 402
Gain
Phase
Av = -10
Rf = 250
Av = -2
Rf = 449
Av = -10
Rf = 250
1M 10M 100M
Frequency (Hz)
180
135
90
45
0
-45
Gain Flatness & Linear Phase
Phase
Vo = 1.5Vpp
PDIP package
Gain
0
-0.2
-0.4
-0.6
-0.8
1M 10M 100M
Frequency (Hz)
Large Signal Pulse Response
Av = +2
Av = -2
Time (20ns/div)
2nd & 3rd Harmonic Distortion, RL = 25
-50
2nd, 10MHz
-60
-70 3rd, 10MHz
-80 2nd, 1MHz
-90
-100 3rd, 1MHz
-110
0
1 2 34
Output Amplitude (Vpp)
Short Term Settling Time
0.2
0.15
0.1
0.05
0
-0.05
-0.1
-0.15
-0.2
1
10 100 1000
Time (ns)
5
10000
-1.0
0 5 10 15 20 25 30
Frequency (MHz)
Differential Gain & Phase
-0.01
f = 3.58MHz
-0.02
Gain Pos Sync
-0.03
-0.04
Phase Neg Sync
-0.02
-0.04
-0.06
-0.08
-0.05
-0.06
-0.07
Gain Neg Sync
Phase Pos Sync
-0.1
-0.12
-0.14
-0.08
1
23
Number of 150 Loads
-0.16
4
2nd & 3rd Harmonic Distortion, RL = 100
-50
2nd, 10MHz
-60
3rd, 10MHz
-70
-80 2nd, 1MHz
-90
-100 3rd, 1MHz
-110
0
0.5 1 1.5 2
Output Amplitude (Vpp)
Long Term Settling Time
0.2
0.15
0.1
0.05
0
-0.05
-0.1
-0.15
-0.2
1µ
10µ 100µ
Time (s)
1m
5
2.5
10m
Frequency Response vs. RL
Vo = 1.5Vpp
PDIP Package
RL = 1k
Gain
Phase
RL = 100
RL = 25
1M 10M 100M
Frequency (Hz)
0
-90
-180
-270
-360
-450
Small Signal Pulse Response
Av = +1
Av = -1
Time (10ns/div)
2nd & 3rd Harmonic Distortion
-60
Vo = 2Vpp
3rd
RL = 100
2nd
-70 RL = 100
-80
-90
-100
1
2nd
RL = 1k
3rd
RL = 1k
Frequency (MHz)
10
2nd & 3rd Harmonic Distortion, RL = 1k
-50
-60 3rd, 10MHz
-70
2nd, 1MHz
-80 2nd, 10MHz
-90 3rd, 1MHz
-100
-110
0
1 2 34
Output Amplitude (Vpp)
IBI, IBN, VOS vs. Temperature
1.6
1.4 IBI
5
7
5
1.2 3
1.0 1
VOS
0.8 -1
0.6
0.4
-60
IBN
-20 20 60
Temperature (°C)
-3
-5
100
http://www.national.com

5 Page





CLC5632 arduino
Rg2
Vin
Rt1
Vd/2
+
1/3
CLC5623
-
Rf1
Rg1 Rt2
Rf2
-
1/3
CLC5623
+
-Vd/2
Rm/2
Req
Rm/2
1:n
Zo
UTP
Io
RL
+
Vo
-
Figure 17: Differential Line Driver wtih
Load Impedance Conversion
Set up the CLC5623 as a difference amplifier:
Vd
Vin
=2
1+
Rf1
Rg1

= 2 Rf2
Rg2
Make the best use of the CLC5623’s output drive
capability as follows:
Rm
+ Req
=
2 Vmax
Imax
where Req is the transformed value of the load imped-
ance, Vmax is the Output Voltage Range, and Imax is the
maximum Output Current.
Match the line’s characteristic impedance:
RL = Zo
Rm = Req
n = RL
Req
Select the transformer so that it loads the line with a
value very near Zo over frequency range. The output
impedance of the CLC5623 also affects the match. With
an ideal transformer we obtain:
Return Loss = −20 log10
n2 Zo(5623)(jω)
Zo
,dB
Bandpass Filter
Figure 18 illustrates a low-sensitivity bandpass filter and
design equations. This topology utilizes the CLC5623’s
closely matched amplifiers to obtain low op-amp
sensitivity at high frequencies. The third CLC5623 is
used as a buffer to obtain low output impedance. The
overall circuit gain is unity. For additional gain, the third
CLC5623 can be configured as a non-inverting amplifier.
To design the filter, choose C and then determine values for
R and R1 based on the desired resonant frequency (fr)
and Q factor.
+
1/3
CLC5623
-
R
C
R
R
R
Vin R1
C
R= 1
2πfrC
R1 = QR
-
1/3
CLC5623
+
+
1/3
CLC5623
-
Rf
Vo
Figure 18: Bandpass Filter Topology
Instrumentation Amplifier
An instrumentation circuit is shown on the front page and
reproduced in Figure 19. The DC CMRR can be fine
tuned by adjusting R1.
V1 +
1/3
CLC5623
-
750
750
V2
750
-
1/3
CLC5623
+
750
750
750
-
1/3
CLC5623
+
R1
750
Vout = 3(V2 - V1)
where Zo(5623)(jω) is the output impedance of the
CLC5623 and |Zo(5623)(jω)| << Rm.
The load voltage and current will fall in the ranges:
Vo n Vmax
Io
Imax
n
The CLC5623’s high output drive current and low
distortion make it a good choice for this application.
Figure 19: Instrumentation Amplifier
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