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PDF CLC5526PCASM Data sheet ( Hoja de datos )
| Número de pieza | CLC5526PCASM | |
| Descripción | Digital Variable Gain Amplifier (DVGA) | |
| Fabricantes | National Semiconductor | |
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June 1999
CLC5526
Digital Variable Gain Amplifier (DVGA)
General Description
The CLC5526 is a high performance, digitally controlled,
variable-gain amplifier (DVGA). It has been designed for use
in a broad range of mixed signal and digital communication
applications such as mobile radio, cellular base stations and
back-channel modems where automatic-gain-control (AGC)
is required to increase system dynamic range.
The CLC5526 has differential input and output, allowing
large signal swings on a single 5V rail. The input impedance
is 200Ω. The differential output impedance is 600Ω and is
designed to drive a 1 kΩ differential load. The output ampli-
fier has excellent intermodulation performance. The
CLC5526 is designed to accept signals from RF elements
and maintain a terminated impedance environment.
The CLC5526 maintains a 350 MHz bandwidth over its en-
tire gain and attenuation range from +30 dB to −12 dB. Inter-
nal clamping ensures very fast overdrive recovery. Two tone
intermodulation distortion is excellent: at 150 MHz, 1 Vpp it is
−64 dBc.
Input signals to the CLC5526 are scaled by an accurate, dif-
ferential R-2R resistive ladder with an input impedance of
200Ω. A scaled version of the input is selected under digital
control and passed to the internal amplifier. The input com-
mon mode level is set at 2.4V via a bandgap referenced bias
generator which can be overridden by an external input.
Following the resistive ladder is a fixed, 30 dB gain amplifier.
The output stage common mode voltage of the CLC5526 is
set to 3V, by internal, positive supply connected resistors.
Digital control of the CLC5526 is accomplished by a 3-bit
parallel gain control input and a data valid pin to latch the
data. If the data is not latched, the DVGA is transparent to
gain control updates. All digital inputs are TTL/CMOS com-
patible.
A shutdown input reduces the CLC5526 supply currrent to a
few mA. During shutdown, the input termination is main-
tained and current attenuation settings are held.
The CLC5526 operates over the industrial temperature
range of −40˚C to +85˚C. The part is available in a 20-pin
SSOP package.
Features
n 350 MHz bandwidth
n Differential input and output
n Gain control: parallel w/data latching
n Supply voltage: +5V
n Supply current: 48 mA
Key Specifications
n Low two tone intermod:
distortion: −64 dBc @ 1 VPP, 150 MHz
24.5 dBm IP3, 150 MHz
n Low noise: 2.5 nV/√Hz (max gain),
9.3 dB noise figure (max gain)
n Wide gain range: +30 dB to −12 dB
n Gain step size: 6 dB
Applications
n Cellular/PCS base stations
n IF sampling receivers
n Infrared/CCD imaging
n Back-channel modems
n Electro-optics
n Instrumentation
n Medical imaging
n High definition video
Block Diagram
© 1999 National Semiconductor Corporation DS015016
DS015016-2
www.national.com
1 page  
Typical Performance Characteristics (VCC = +5V, RL = 1 kΩ, max gain; unless
specified) (Continued)
6 dB Gain Step, Time Domain
Response
Gain Step Error Deviation
vs Gain Setting
Input Referred Thermal Noise vs
Gain Setting (Gain Block)
DS015016-9
Noise Figure vs Gain Setting
DS015016-10
Differential ZIN vs Frequency
DS015016-11
Differential ZOUT vs Frequency
DS015016-12
DS015016-13
DS015016-14
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