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PDF CLC533AJE Data sheet ( Hoja de datos )

Número de pieza CLC533AJE
Descripción High-Speed 4:1 Analog Multiplexer
Fabricantes National Semiconductor 
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N
CLC533
High-Speed 4:1 Analog Multiplexer
June 1999
General Description
The CLC533 is a high-speed 4:1 multiplexer employing active
input and output stages. The CLC533 also employs a closed-loop
design which dramatically improves accuracy over conventional
analog multiplexer circuits. This monolithic device is constructed
using an advanced high-performance bipolar process.
The CLC533 has been specifically designed to provide a 24ns
settling time to 0.01%. This coupled with the adjustable band-
width, makes the CLC533 an ideal choice for infrared and CCD
imaging systems, with channel-to-channel isolation of 80dB @
10MHz. Low distortion and spurious signal levels (-80dBc) make
the CLC533 a very suitable choice for I/Q processors in radar
receivers.
The CLC533 is offered over both the industrial and military tem-
perature ranges. The industrial versions, CLC533AJP\AJE\AIB,
are specified from -40°C to +85°C and are packaged in 16-pin
plastic DIPs, SOIC’s and CERDIP packages. The extended tem-
perature versions, CLC533A8B/A8L-2A, are specified from -55°C
to +125°C and are packaged in 16-pin CERDIP and 20-terminal
LCC packages.
Ordering Information ...
CLC533AJP
-40°C to +85°C 16-pin plastic DIP
CLC533AJE
-40°C to +85°C 16-pin plastic SOIC
CLC533ALC
-40°C to +85°C
dice
CLC533A8B
-55°C to +125°C 16-pin CERDIP,
MIL-STD-883
CLC533AMC
-40°C to +85°C
dice, MIL-STD-833
CLC533A8L-2A -55°C to +125°C 20-terminal LCC,
MIL-STD-883
Contact factory for other packages and DESC SMD number.
Features
s 12-bit settling (0.01%) – 17ns
s Low noise – 42µVrms
s Isolation – 80dB @ 10MHz
s 110MHz -3dB bandwidth (Av = +2)
s Low distortion – 80dB @ 5MHz
s Adjustable bandwidth – 180MHz (max)
Applications
s Infrared system multiplexing
s CCD sensor signals
s Radar I/Q switching
s High definition video HDTV
s Test and calibration
87654
GND 9
IND 10
NC 11
Vee 12
A1 13
14 15 16 17 18
3 INA
2 GND
1 NC
20 OUTPUT
19 COMP1
Functional Diagram
A1 A0
00
01
10
11
OUT
A
B
C
D
ECL Mode - DREF = open
TTL Mode - DREF = +5V
Pinout
DIP & SOIC
© 1999 National Semiconductor Corporation
Printed in the U.S.A.
http://www.national.com

1 page




CLC533AJE pdf
Recommended Operating Conditions
positive supply voltage (+Vcc)
negative supply voltage (-Vee)
differential voltage between any two GND’s
+5.0V
-5.2V
10mV
analog input voltage range
±2V
AX input voltage range (TTL mode)
AX input voltage range (ECL mode)
CCOMP range 5pF to 100pF
0V to +5.0V
0V to -2.0V
thermal data
16-pin plastic
θjc(°C/W)
50
16-pin Cerdip
20
16-pin SOIC
60
20-terminal LCC 20
16-pin side brazed 20
θja(°C/W)
60
65
75
35
50
Note 1: Test levels are as follows:
* AJ : 100% tested at +25°C.
Note 2: Settling time measured from the 50% analog output
transition.
Note 3: Absolute maximum ratings are limiting values, to be
applied individually, and beyond which the serviceability of the cir-
Reliability Information
Transistor count
144
Absolute Maximum Ratings3
positive supply voltage (+Vcc)
-0.5V to +7.0V
negative supply voltage (-Vee)
+0.5V to -7.0V
differential voltage between any two GND’s
200mV
analog input voltage range
-Vee to +Vcc
digital input voltage range
-Vee to +Vcc
output short circuit duration (shorted to GND)
Infinite
junction temperature
+150°C
operating temperature range
CLC533AJP/AJE/AIB
-40°C to +85°C
storage temperature range
-65°C to +150°C
lead solder duration (+300°C)
10 sec
ESD rating (human body model)
<500V
cuit may be impaired. Functional operability under any of these
conditions is not necessarily implied. Exposure to maximum rat-
ings for extended periods may affect device reliability.
Package Thermal Resistance
Package
AJP
AJE
CERDIP
θJC
45°C/W
35°C/W
25°C/W
θJA
95°C/W
100°C/W
65°C/W
System Timing Diagram
Switching Transient Timing Diagram
APPLICATIONS INFORMATION
Operation
The CLC533 is a 4:1 analog multiplexer designed with a
closed loop architecture to provide very low harmonic
distortion and superior channel to channel isolation. This
low distortion, coupled with very fast switching
speed make the CLC533 an ideal multiplexer for data
conversion applications. User selectable ECL or TTL
select logic adds to the versatility of this device. External
frequency response compensation allows the
performance of the CLC533 to be optimized for each
application.
Digital Interface and Channel Select
The CLC533 has two channel select pins which can be
used to select any one of the four inputs. These
digital inputs can be configured to meet TTL, ECL or
CMOS logic levels with the DREF pin. If DREF is left
open, then the A0 and A1 select inputs will respond to
ECL 10K switching levels (Figure 1). For TTL or CMOS
levels, DREF should be tied to Vcc (Figure 2). There is an
internal series resistor which makes it possible to
connect DREF directly to the power supply. Select pins
according to the truth table shown on the front page. A
more positive voltage is considered to be a logic ‘1’.
Therefore with no connection to A0 or A1 the internal pull-
up resistors will select the D input to be passed through
to the output.
Compensation
The CLC533 is externally compensated, allowing
the user to select the bandwidth that best suits
the application. Decreasing bandwidth has two
advantages: lower noise and lower switching tran-
sients. In a sampled system, noise at frequencies
5 http://www.national.com

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