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Número de pieza CLC431
Descripción Dual Wideband Monolithic Op Amp with Disable
Fabricantes National Semiconductor 
Logotipo National Semiconductor Logotipo



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N
CLC431/432
Dual Wideband Monolithic Op Amp with Disable
June 1999
General Description
The CLC431 and CLC432 current-feedback amplifiers provide wide
bandwidths and high slew rates for applications where board density
and power are key considerations. These amplifiers provide DC-
coupled small signal bandwidths exceeding 92MHz while consuming
only 7mA per channel. Operating from ±15V supplies, the CLC431/
432’s enhanced slew rate circuitry delivers large-signal bandwidths
with output voltage swings up to 28Vpp. A wide range of bandwidth-
insensitive gains are made possible by virtue of the CLC431 and
CLC432’s current-feedback topology.
The large common-mode input range and fast settling time (70ns
to 0.05%) make these amplifiers well suited for CCD & data
telecommunication applications. The disable of the CLC431 can
accommodate ECL or TTL logic levels or a wide range of user
definable inputs. With its fast enable/disable time (0.2µs/1µs) and
high channel isolation of 70dB at 10MHz, the CLC431 can easily be
configured as a 2:1 MUX. Many high performance video applications
requiring signal gain and/or switching will be satisfied with the
CLC431/432 due to their very low differential gain and phase errors
(less than 0.1% and 0.1°; Av = +2V/V at 4.43MHz into 150load).
Quick 8ns rise and fall times on 10V pulses allow the CLC431/432 to
drive either twisted pair or coaxial transmission lines over long
distances.
The CLC431/432's combination of low input voltage noise, wide
common-mode input voltage range and large output voltage swings
make them especially well suited for wide dynamic range signal
processing applications.
Features
s Wide bandwidth: 92MHz (A =+1)
V
62MHz (Av=+2)
s Fast slew rate: 2000V/µs
s Fast disable: 1µs to high-Z output
s High channel isolation: 70dB at 10MHz
s Single or dual supplies: ±5V to ±16.5V
Applications
s Video signal multiplexing
s Twisted-pair differential driver
s CCD buffer & level shifting
s Discrete gain-select amplifier
s Transimpedance amplifier
Typical Application
Discrete Gain Select Amplifier
1Vpp @ 5MHz
Rg 500
Rf Channel 1 (Gain = 2)
500
50
SELECT
50
½CLC431
Ri
50
½CLC431
Ri
50
Rs
50
50
Vout
RL
500
Rf
Rg 125
Channel 2 (Gain = 5)
Pinout
PDIP & SOIC
CLC431
Vinv1 1
Vnon-inv1 2
DIS1 3
-Vcc 4
DIS2 5
Vnon-inv2 6
Vinv2 7
14 Vout1
13 VRTTL1
12 DIS1
11 +Vcc
10 DIS2
9 VRTTL2
8 Vout2
Vout1
Vinv1
Vnon-inv1
-Vcc
1
2
3
4
CLC432
-
+
-
+
8 +Vcc
7 Vout2
6 Vinv2
5 Vnon-inv2
© 1999 National Semiconductor Corporation
Printed in the U.S.A.
http://www.national.com

1 page




CLC431 pdf
front page). Also note that both amplifiers are guaranteed
to be enabled if all three of these pins are unconnected.
Fig. 1 illustrates the single-ended mode of the CLC431's
disable feature for logic families such as TTL and CMOS.
In order to operate properly, VRTTL must be grounded,
thereby biasing DIS to approximately +1.4V through the
two internal series diodes. For single-ended operation,
DIS should be left floating. Applying a TTL or CMOS logic
"high" (i.e. >2.0Volts) to DIS will switch the tail current of
the differential pair to Q1 and "shut down" Q2 which
results in the disabling of that channel of the CLC431.
Alternatively, applying a logic "low" (i.e. <0.8Volts) to DIS
will switch the tail current from Q1 to Q2 effectively
enabling that channel. If DIS is left floating under single-
ended operation, then the associated amplifier is guaran-
teed to be disabled.
Vnon-inv
Vinv
TTL
CMOS
DIS
+
-
+VCC
+VCC
+VCC
100k
Q1
100k
Q2
Vout
DIS
VRTTL
Fig. 2 illustrates the differential mode of the CLC431's
disable feature for ECL-type logic. In order for this mode
to operate properly, VRTTL must be left floating while DIS
and DIS are to be connected directly to the ECL gate as
illustrated. Applying a differential logic "high" (DIS - DIS
0.4Volts) switches the tail current of the differential pair
from Q2 to Q1 and results in the disabling of that CLC431
channel. Alternatively, applying a differential logic "low"
(DIS - DIS -0.4Volts) switches the tail current of the
differential pair from Q1 to Q2 and results in the enabling
of that same channel. The internal clamp, mentioned
above, also protects against excessive differential volt-
ages up to 30Volts while limiting input currents to <3mA.
DC Performance
A current-feedback amplifier’s input stage does not have
equal nor correlated bias currents, therefore they cannot
be cancelled and each contributes to the total DC offset
voltage at the output by the following equation:
Voffset
=
±

Ibn
Rs
1+
Rf
Rg

+
Vio
1+
Rf
Rg

+
Ibi
Rf

The input resistor Rs is that resistance seen when looking
from the non-inverting input back towards the source. For
inverting DC-offset calculations, the source resistance
seen by the input resistor Rg must be included in the
output offset calculation as a part of the non-inverting
gain equation. Application note OA-7 gives several circuits
for DC offset correction.
½CLC431
Fig. 1
The disable feature of the CLC431 is such that DIS and
DIS have common-mode input voltage ranges of (+VCC)
to (-VCC+3V) and are so guaranteed over the commercial
temperature range. Internal clamps (not shown) protect
the DIS input from excessive input voltages that could
otherwise cause damage to the device. This condition
occurs when enough source current flows into the node
so as to allow DIS to rise to VCC. This clamp is activated
once DIS exceeds DIS by 1.5Volts and guarantees that
VDIS (ground referenced) does not exceed 4.7Volts.
Vnon-inv
Vinv
+
Vout
-
+VCC
+VCC
+VCC
ECL
DIS
510
100k
Q1
-5V ½CLC431
100k
Q2
DIS
VRTTL
510
-5V
Fig. 2
Layout Considerations
It is recommended that the decoupling capacitors (0.1µF
ceramic and 6.8µF electrolytic) should be placed as close
as possible to the power supply pins to insure a proper
high-frequency low impedance bypass. Careful attention
to circuit board layout is also necessary for best
performance. Of particular importance is the control of
parasitic capacitances (to ground) at the output and
invering input pins. See CLC431/432 Evaluation Board
literature for more information.
Applications Circuits
2:1 Video Mux (CLC431)
Fig. 3 illustrates the connections necessary to configure
the CLC431 as a 2:1 multiplexer in a 75system. Each
of the two CLC431's amplifiers is configured with a non-
inverting gain of +2V/V using 634feedback (Rf) and
gain-setting (Rg) resistors. The feedback resistor value is
lower than that recommended in order to compensate for
the reduction of loop-gain that results from the inclusion
of the 50resistor (Ri) in the feedback loop. This 50
resistor serves to isolate the output of the active channel
from the impedance of the inactive channel yet does not
affect the low output impedance of the active channel.
Notice that for proper operation VRTTL1(pin 13) is grounded
and VRTTL 2 (pin 9) is unconnected. The pins associated
with the disable feature are to be connected as follows:
DIS1 and DIS2 (pins 3 & 10) are connected together as
well as DIS2 and DIS1 (pins 5 & 12). Channel 1 is
selected with the application of a logic "low" to SELECT
while a logic "high" selects Channel 2.
5 http://www.national.com

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