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PDF CLC418 Data sheet ( Hoja de datos )

Número de pieza CLC418
Descripción Dual High-Speed/ Low-Power Line Driver
Fabricantes National Semiconductor 
Logotipo National Semiconductor Logotipo



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N
Comlinear CLC418
Dual High-Speed, Low-Power Line Driver
August 1996
General Description
The Comlinear CLC418 dual high-speed current-feedback
operational amplifier is designed to drive low-impedance and
high capacitance loads while maintaining high signal fidelity.
Operating on ±5V power supplies, each of the CLC418’s
amplifiers produces a continuous 96mA output current. Into a
back-terminated 50load, the devices produce -85/-64dBc
second/third harmonic distortion (Av = +2, Vo = 2Vpp, f = 1MHz).
The CLC418’s current-feedback architecture maintains consistent
performance over a wide range of gain and signal levels. DC gain
and bandwidth can be set independently. With proper resistor
selection, either maximally flat gain response or linear phase
response can be selected.
Requiring a mere 15mW quiescent power per amplifier, the
CLC418 offers superior performance-vs-power with a 130MHz
small-signal bandwidth, 350V/ms slew rate and quick 4.6ns
rise/fall times (2Vstep). The combination of low quiescent power,
high output current drive and high performance make the
CLC418 a great choice for many battery-powered personal
communication/computing systems.
Combining the CLC418’s two amplifiers (shown below) results in
a powerful differential line driver for driving video signals over
unshielded twisted-pair (UTP). The CLC418 can also be used for
driving differential-input step-up transformers for applications
such as Asynchronous Digital Subscriber Lines (ADSL) or High-
Bit-Rate Digital Subscriber Lines (HDSL).
The CLC418’s amplifiers make excellent low-power high-
resolution A-to-D converter drivers with their very fast 15ns set-
tling time (to 0.2%) and ultra-low -85/-75dBc harmonic distortion
(Av = +2, Vo = 2Vpp, f = 1MHz, RL = 1k).
Typical Application Diagram
Differential Line Driver
with Load Impedance Conversion
Features
s 130MHz bandwidth (Av = +2)
s 96mA output current
s 1.5mA supply current
s -85/-75dBc HD2/HD3
s 15ns settling to 0.2%
s -74dBc input-referred crosstalk (5MHz)
s Single version available (CLC408)
Applications
s ADSL/HDSL driver
s Coaxial cable driver
s UTP differential line driver
s Transformer/coil driver
s High capacitive-load driver
s Video line driver
s Portable/battery-powered line driver
s Differential A/D driver
Non-Inverting Frequency Response
(Av = +2V/V, RL = 100)
1M 10M 100M
Frequency (Hz)
418 Freq. Resp. Plot
Pinout
DIP & SOIC
Rg2
Vin
Rt1
Vd/2
+
1/2
CLC418
-
Rf1
Rg1 Rt2
Rf2
-
1/2
CLC418
+
-Vd/2
Rm/2
Req
Rm/2
I:n
Zo
UTP
Io
RL
+
Vo
-
Vo1
Vinv1
Vnon-inv1
VEE
VCC
Vo2
Vinv2
Vnon-inv2
418 Typ App Diag
418 Pinout
© 1996 National Semiconductor Corporation
Printed in the U.S.A.
http://www.national.com

1 page




CLC418 pdf
CLC418 OPERATION
The CLC418 has a current-feedback (CFB) architecture
built in an advanced complementary bipolar process.
The key features of current-feedback are:
s AC bandwidth is independent of voltage gain
s Inherently unity-gain stability
s Frequency response may be adjusted with
feedback resistor (Rf in Figures 1-3)
s High slew rate
s Low variation in performance for a wide range
of gains, signal levels and loads
s Fast settling
Current-feedback operation can be explained with a
simple model. The voltage gain for the circuits in Figures 1
and 2 is approximately:
Vo
Vin
=
Av
1+
Rf
Z(jω)
where:
s Av is the DC voltage gain
s Rf is the feedback resistor
s Z(jω) is the CLC418’s open-loop
transimpedance gain
s Z(jω) is the loop gain
Rf
The denominator of the equation above is approximately
1 at low frequencies. Near the -3dB corner
frequency, the interaction between Rf and Z(jω)
dominates the circuit performance. Increasing Rf does
the following:
s Decreases loop gain
s Decreases bandwidth
s Reduces gain peaking
s Lowers pulse response overshoot
s Affects frequency response phase linearity
CLC418 DESIGN INFORMATION
Standard op amp circuits work with CFB op amps. There
are 3 unique design considerations for CFB:
s The feedback resistor (Rf in Figures 1-3) sets
AC performance
s Rf cannot be replaced with a short or a capacitor
s The output offset voltage is not reduced by
balancing input resistances
The following sub-sections cover:
s Design parameters, formulas and techniques
s Interfaces
s Application circuits
s Layout techniques
s SPICE model information
DC Gain (non-inverting)
The non-inverting DC voltage gain for the configuration
shown in Figure 1 is:
Av
= 1+
Rf
Rg
VCC
6.8µF
+
Vin
Rt
3(5) + 8 0.1µF
1/2 1(7)
2(6)
CLC418
-
4 Rf
Rg 0.1µF
Vo
+
6.8µF
VEE
418 Fig1
Figure 1: Non-Inverting Gain
The normalized gain plots in the Typical Performance
Characteristics section show different feedback
resistors (Rf) for different gains. These values of Rf are
recommended for obtaining the highest bandwidth with
minimal peaking. The resistor Rt provides DC bias for
the non-inverting input.
For Av < 6, use linear interpolation on the nearest Av
values to calculate the recommended value of Rf. For Av
6, the minimum recommended Rf is 200.
Select Rg to set the DC gain:
Rg
=
Rf
Av 1
DC gain accuracy is usually limited by the tolerance of Rf
and Rg.
DC Gain (unity gain buffer)
The recommended Rf for unity gain buffers is 3k. Rg is
left open. Parasitic capacitance at the inverting node
may require a slight increase of Rf to maintain a flat
frequency response.
DC Gain (inverting)
The inverting DC voltage gain for the configuration
shown in Figure 2 is:
Av
=
Rf
Rg
The normalized gain plots in the Typical Performance
Characteristics section show different feedback
resistors (Rf) for different gains. These values of Rf are
recommended for obtaining the highest bandwidth with
minimal peaking. The resistor Rt provides DC bias for
the non-inverting input.
For |Av| < 6, use linear interpolation on the nearest Av
values to calculate the recommended value of Rf. For
|Av| 6, the minimum recommended Rf is 200.
5 http://www.national.com

5 Page





CLC418 arduino
Calculate all other resistor values:
R1
=
R2
G1
R5
=
R7
G2
R6
=
R5
1+
R4
R6

R4 = R5 R6
Notice that R4 and R6 are selected so that U1a and the
diodes see a balanced load for both polarities of Vin.
The capacitor C1 is optional. It helps compensate for the
difference between the gains Vo/V1 and Vo/V2 at high
frequencies. Both R4 and R6 must be > 0.
We built and tested a full-wave rectifier with the
following values:
s D1 = D2 = Schottky Diodes,
Digi-Key # SD101ACT-ND
s R2 = R3 = R7 = 1.00k
s R1 = 1.00k
s R5 = 1.50k
s R6 = 882
s R4 = 618
The rectifier had equal inverting and non-inverting gains
for frequencies less than 10MHz. The -3dB bandwidth
was about 25MHz.
Ordering Information
Model
Temperature Range
CLC418AJP
CLC418AJE
CLC418AJE-TR
CLC418AJE-TR13
CLC418ALC
-40˚C to +85˚C
-40˚C to +85˚C
-40˚C to +85˚C
-40˚C to +85˚C
-40˚C to +85˚C
Description
8-pin PDIP
8-pin SOIC
8-pin SOIC, 750pc reel
8-pin SOIC, 2500pc reel
dice (commercial)
Package Thermal Resistance
Package
Plastic (AJP)
Surface Mount (AJE)
qJC
80˚C/W
95˚C/W
qJA
95˚C/W
115˚C/W
Reliability Information
Transistor Count
MTBF (based on limited test data)
76
34Mhr
11 http://www.national.com

11 Page







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