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PDF CLC411AMC Data sheet ( Hoja de datos )

Número de pieza CLC411AMC
Descripción High-Speed Video Op Amp with Disable
Fabricantes National Semiconductor 
Logotipo National Semiconductor Logotipo



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N
CLC411
High-Speed Video Op Amp with Disable
June 1999
General Description
The CLC411 combines a state-of-the-art complementary bipolar
process with National’s patented current-feedback architecture to
provide a very high-speed op amp operating from ±15V supplies.
Drawing only 11mA quiescent current, the CLC411 provides a
200MHz small signal bandwidth and a 2300V/µs slew rate while
delivering a continuous 70mA current output with ±4.5V output swing.
The CLC411’s high-speed performance includes a 15ns settling time
to 0.1% (2V step) and a 2.3ns rise and fall time (6V step).
The CLC411 is designed to meet the requirements of professional
broadcast video systems including composite video and high definition
television. The CLC411 exceeds the HDTV standard for gain flatness
to 30MHz with it's ±0.05dB flat frequency response and exceeds
composite video standards with its very low differential gain and
phase errors of 0.02%, 0.03°. The CLC411 is the op amp of choice
for all video systems requiring upward compatibility from NTSC and
PAL to HDTV.
The CLC411 features a very fast disable/enable (10ns/55ns) allowing
the multiplexing of high-speed signals onto an analog bus through the
common output connections of multiple CLC411’s. Using the same
signal source to drive disable/enable pins is easy since “break-
before-make” is guaranteed.
The CLC411 is available in several versions:
CLC411AJP
CLC411AJE
CLC411A8B
-40°C to +85°C
-40°C to +85°C
-55°C to +125°C
CLC411AMC -55°C to +125°C
DESC SMD number: 5962-94566
8-pin plastic DIP
8-pin plastic SOIC
8-pin hermetic CERDIP,
MIL-STD-883
dice, MIL-STD-883, Level B
Features
s 200MHz small signal bandwidth (1V )
pp
s ±0.05dB gain flatness to 30MHz
s 0.02%, 0.03° differential gain, phase
s 2300V/µs slew rate
s 10ns disable to high-impedance output
s 70mA continuous output current
s ±4.5V output swing into 100load
s ±4.0V input voltage range
Applications
s HDTV amplifier
s Video line driver
s High-speed analog bus driver
s Video signal multiplexer
s DAC output buffer
Gain Flatness (Av=+2)
0
Frequency (5MHz/div)
50
Recommended
Inverting Gain
Configuration
Vin
RT
© 1999 National Semiconductor Corporation
Printed in the U.S.A.
25
Rg
+Vcc
6.8µF
0.1µF
DIS
7 +Vr
3+ 8 1
CLC411
0.01µF
6
2_
4
5 0.01µF
-Vr
Vout
0.1µF
6.8µF
-Vcc
Rf
Select RT to yield
Rin = RT||Rg
Pinout
DIP & SOIC
+Vr 1
Vinv 2
Vnon-inv 3
-Vcc 4
-
+
8 DIS
7 +Vcc
6 Vout
5 -Vr
http://www.national.com

1 page




CLC411AMC pdf
non-zero Rf must be used with current-feedback
operational amplifiers such as the CLC411. Application
note OA-13, “Current-Feedback Loop-Gain Analysis
and Performance Enhancements,” explains the
ramifications of Rf and how to use it to tailor the desired
frequency response with respect to gain. The equations
found in the application note should be considered as a
starting point for the selection of Rf. The equations do
not factor in the effects of parasitic capacitance found
on the inverting input, the output nor across the feedback
resistor. Equations in OA-13 require values for Rf
(301), Av (+2) and Ri (inverting input resistance, 50).
Combining these values yields a Zt* (optimum feedback
transimpedance) of 400. Figure 4 entitled
"Recommended Rf vs. Gain" will enable the selection of
the feedback resistor that provides a maximally flat
frequency response for the CLC411 over its gain range.
The linear portion of the two curves (i.e. AV>4) results
from the limitation on Rg (i.e. Rg 50).
Enable/Disable Operation
The disable feature allows the outputs of several CLC411
devices to be connected onto a common analog bus
forming a high-speed analog multiplexer. When disabled,
the output and inverting inputs of the CLC411 become
high impedances. The disable pin has an internal pull-
up resistor which is pulled-up to an internal voltage, not
to the external supply. The CLC411 is enabled when pin
8 is left open or pulled-up to +7V and disabled when
grounded or pulled below +3V. CMOS logic devices are
necessary to drive the disable pin. For example, CMOS
logic with VDD +7V will guarantee proper operation over
temperature. TTL voltage levels are inadequate for
controlling the disable feature.
+15V
0.1µF
Q3 Q4
CLC411 pin 8, DISABLE
Disable
Q1
Q2 Vth
3.57k
0.1µF
Q1,Q2 MPSH10
Q3,Q4 MPSH81
-15V
Figure 5A: Disable Interface
Q1 Q2
330
330
-5.2V
-5.2V
ECL
Gate
Figure 5B: Differential ECL Interface
For faster enable/disable operation than 15V CMOS
logic devices will allow, the circuit of Figure 5 is
recommended. A fast four-transistor comparator, Figure
5A, interfaces between the CLC411 DISABLE pin and
several standard logic families. This circuit has a
differential input between the bases of Q1 and Q2. As
such it may be driven directly from differential ECL
logic, as in shown in Figure 5B. Single-ended logic
families may also be used by establishing an appropriate
threshold voltage on the Vth input, the base of Q2.
A0
B1
C2
3
4
5
6
7
Buffers
DIS (pin 8)
+
A
-
CLC411
ECL
Gate
Q1
330
Q2 50
931
10k
0.1µF
-5.2V
-15V
Figure 5C: ECL Interface
50
TTL
Gate
Q1 Q2
332
500.1µF
1N914
Figure 5D: TTL Interface
DIS (pin 8)
+
B
- CLC411
Figure 6: General Multiplexing Circuit
Figures 5C and 5D illustrate a single-ended ECL and
TTL interface respectively. The Disable input, the base
of Q1, is driven above and below the threshold, Vth.
Fastest switching speeds result when the differential
voltage between the bases of Q1 and Q2 is kept to less
5 http://www.national.com

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