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PDF NT5DS128M4CS Data sheet ( Hoja de datos )

Número de pieza NT5DS128M4CS
Descripción 512Mb DDR SDRAM
Fabricantes Nanya Techology 
Logotipo Nanya Techology Logotipo



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NT5DS32M16CG
NT5DS64M8CG
NT5DS128M4CG
NT5DS32M16CS
NT5DS64M8CS
NT5DS128M4CS
512Mb DDR SDRAM
Features
• DDR 512M bit, Die C, based on 90nm design rules
• Double data rate architecture: two data transfers per
clock cycle
• Bidirectional data strobe (DQS) is transmitted and
received with data, to be used in capturing data at the
receiver
• DQS is edge-aligned with data for reads and is center-
aligned with data for writes
• Differential clock inputs (CK and CK)
• Four internal banks for concurrent operation
• Data mask (DM) for write data
• DLL aligns DQ and DQS transitions with CK transitions
• Commands entered on each positive CK edge; data and
data mask referenced to both edges of DQS
• Burst lengths: 2, 4, or 8
• CAS Latency: 2.5, 3
• Auto Precharge option for each burst access
• Auto Refresh and Self Refresh Modes
• 7.8µs Maximum Average Periodic Refresh Interval
• 2.5V (SSTL_2 compatible) I/O
• VDD = VDDQ = 2.6V ± 0.1V (DDR400)
• VDD = VDDQ = 2.5V ± 0.2V (DDR333)
• RoHS compliance
Description
Die C of 512Mb SDRAM devices based using DDR interface.
They are all based on Nanya’s 90 nm design process.
The 512Mb DDR SDRAM is a high-speed CMOS, dynamic
random-access memory containing 536,870,912 bits. It is
internally configured as a quad-bank DRAM.
The 512Mb DDR SDRAM uses a double-data-rate architec-
ture to achieve high-speed operation. The double data rate
architecture is essentially a 2n prefetch architecture with an
interface designed to transfer two data words per clock cycle
at the I/O pins. A single read or write access for the 512Mb
DDR SDRAM effectively consists of a single 2n-bit wide, one
clock cycle data transfer at the internal DRAM core and two
corresponding n-bit wide, one-half-clock-cycle data transfers
at the I/O pins.
A bidirectional data strobe (DQS) is transmitted externally,
along with data, for use in data capture at the receiver. DQS
is a strobe transmitted by the DDR SDRAM during Reads
and by the memory controller during Writes. DQS is edge-
aligned with data for Reads and center-aligned with data for
Writes.
The 512Mb DDR SDRAM operates from a differential clock
(CK and CK; the crossing of CK going high and CK going
LOW is referred to as the positive edge of CK). Commands
(address and control signals) are registered at every positive
edge of CK. Input data is registered on both edges of DQS,
and output data is referenced to both edges of DQS, as well
as to both edges of CK.
Read and write accesses to the DDR SDRAM are burst ori-
ented; accesses start at a selected location and continue for
a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an Active
command, which is then followed by a Read or Write com-
mand. The address bits registered coincident with the Active
command are used to select the bank and row to be
accessed. The address bits registered coincident with the
Read or Write command are used to select the bank and the
starting column location for the burst access.
The DDR SDRAM provides for programmable Read or Write
burst lengths of 2, 4, or 8 locations. An Auto Precharge func-
tion may be enabled to provide a self-timed row precharge
that is initiated at the end of the burst access.
As with standard SDRAMs, the pipelined, multibank architec-
ture of DDR SDRAMs allows for concurrent operation,
thereby providing high effective bandwidth by hiding row pre-
charge and activation time.
An auto refresh mode is provided along with a power-saving
Power Down mode. All inputs are compatible with the JEDEC
Standard for SSTL_2. All outputs are SSTL_2, Class II com-
patible.
The functionality described and the timing specifications
included in this data sheet are for the DLL Enabled mode of
operation.
REV 1.0
Dec 2007
1
© NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

1 page




NT5DS128M4CS pdf
NT5DS32M16CG
NT5DS64M8CG
NT5DS128M4CG
NT5DS32M16CS
NT5DS64M8CS
NT5DS128M4CS
512Mb DDR SDRAM
Pin Configuration - 60 balls 0.8mmx1.0mm Pitch CSP Package
<Top View >
See the balls through the package.
1
VSSQ
DQ14
DQ12
DQ10
DQ8
VREF
2
DQ15
VDDQ
VSSQ
VDDQ
VSSQ
VSS
CLK
A12
A11
A8
A6
A4
3
VSS
DQ13
DQ11
DQ9
UDQS
UDM
CLK
CKE
A9
A7
A5
VSS
32 X 16
A
B
C
D
E
F
G
H
J
K
L
M
7
VDD
DQ2
DQ4
DQ6
LDQS
LDM
WE
RAS
BA1
A0
A2
VDD
8
DQ0
VSSQ
VDDQ
VSSQ
VDDQ
VDD
CAS
CS
BA0
A10/
AP
A1
A3
9
VDDQ
DQ1
DQ3
DQ5
DQ7
NC
REV 1.0
Dec 2007
5
© NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

5 Page





NT5DS128M4CS arduino
NT5DS32M16CG
NT5DS64M8CG
NT5DS128M4CG
NT5DS32M16CS
NT5DS64M8CS
NT5DS128M4CS
512Mb DDR SDRAM
Register Definition
Mode Register
The Mode Register is used to define the specific mode of operation of the DDR SDRAM. This definition includes the selection of
a burst length, a burst type, a CAS latency, and an operating mode. The Mode Register is programmed via the Mode Register
Set command (with BA0 = 0 and BA1 = 0) and retains the stored information until it is programmed again or the device loses
power (except for bit A8, which is self-clearing).
Mode Register bits A0-A2 specify the burst length, A3 specifies the type of burst (sequential or interleaved), A4-A6 specify the
CAS latency, and A7-A12 specify the operating mode.
The Mode Register must be loaded when all banks are idle, and the controller must wait the specified time before initiating the
subsequent operation. Violating either of these requirements results in unspecified operation.
Burst Length
Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable. The burst length
determines the maximum number of column locations that can be accessed for a given Read or Write command. Burst lengths
of 2, 4, or 8 locations are available for both the sequential and the interleaved burst types.
Reserved states should not be used, as unknown operation or incompatibility with future versions may result.
When a Read or Write command is issued, a block of columns equal to the burst length is effectively selected. All accesses for
that burst take place within this block, meaning that the burst wraps within the block if a boundary is reached. The block is
uniquely selected by A1-Ai when the burst length is set to two, by A2-Ai when the burst length is set to four and by A3-Ai when
the burst length is set to eight (where Ai is the most significant column address bit for a given configuration). The remaining
(least significant) address bit(s) is (are) used to select the starting location within the block. The programmed burst length
applies to both Read and Write bursts.
REV 1.0
Dec 2007
11
© NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

11 Page







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