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PDF MACH231-15 Data sheet ( Hoja de datos )
| Número de pieza | MACH231-15 | |
| Descripción | High-Performance EE CMOS Programmable Logic | |
| Fabricantes | Vantis | |
| Logotipo |  |
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1
FINAL
MACH 1 & 2 FAMILIES
COM’L: -6/7/10/12/15 IND: -12/14/18
MACH231-6/7/10/12/15
High-Performance EE CMOS Programmable Logic
DISTINCTIVE CHARACTERISTICS
x 84 Pins in PLCC
x 128 Macrocells
x 6 ns tPD Commercial; 12 ns tPD Industrial
x 133 MHz fCNT
x 64 I/Os; 4 dedicated inputs/clocks; 2 dedicated inputs
x 128 Flip-flops; 4 clock choices
x 8 “PALCE32V16" blocks with buried macrocells
x SpeedLocking™ for guaranteed fixed timing
x Bus-Friendly™ Inputs and I/Os
x Peripheral Component Interconnect (PCI) compliant (-6/-7/-10/-12)
x Programmable power-down mode
x Pin-compatible with the MACH131 and M4-128N
GENERAL DESCRIPTION
The MACH231 is a member of Vantis’ high-performance EE CMOS MACH® 1 & 2 device families.
This device has approximately twelve times the logic macrocell capability of the popular
PALCE22V10 without loss of speed.
The MACH231 consists of eight PAL® blocks interconnected by a programmable switch matrix.
The switch matrix connects the PAL blocks to each other and to all input pins, providing a high
degree of connectivity between the fully-connected PAL blocks. This allows designs to be placed
and routed efficiently.
The MACH231 has two kinds of macrocell: output and buried. The output macrocell provides
registered, latched, or combinatorial outputs with programmable polarity. If a registered
configuration is chosen, the register can be configured as D-type or T-type to help reduce the
number of product terms. The register type decision can be made by the designer or by the
software. All output macrocells can be connected to an I/O cell. If a buried macrocell is desired,
the internal feedback path from the macrocell can be used, which frees up the I/O pin for use
as an input.
The MACH231 has dedicated buried macrocells which, in addition to the capabilities of the
output macrocell, also provide input registers for use in synchronizing signals and reducing
setup time requirements.
Vantis offers software design support for MACH devices through its own development system
and device fitters integrated into third-party CAE tools. Platform support extends across PCs, Sun
and HP workstations under advanced operating systems such as Windows 3.1, Windows 95 and
NT, SunOS and Solaris, and HPUX.
Publication# 19603 Rev: C
Amendment/0
Issue Date: August 1997
1
1 page  
VANTIS
ORDERING INFORMATION
Commercial Products
Vantis programmable logic products for commercial applications are available with several ordering options. The order number
(Valid Combination) is formed by a combination of:
MACH 231 -7 J C
FAMILY TYPE
MACH = Macro Array CMOS High-Speed
DEVICE NUMBER
231 = 128 Macrocells, 84 Pins
SPEED
-6 = 6 ns tPD
-7 = 7.5 ns tPD
-10 = 10 ns tPD
-12 = 12 ns tPD
-15 = 15 ns tPD
PROGRAMMING DESIGNATOR
Blank = Initial Algorithm
/1 = First Revision
OPERATING CONDITIONS
C = Commercial (0°C to +70°C)
PACKAGE TYPE
J = 84-Pin Plastic Leaded
Chip Carrier (PL 084)
Valid Combinations
MACH231-6
MACH231-7
JC
MACH231-10
MACH231-12
JC/1
MACH231-15
Valid Combinations
The Valid Combinations table lists configurations planned to
be supported in volume for this device. Consult the local Vantis
sales office to confirm availability of specific valid
combinations and to check on newly released combinations.
MACH231-6/7/10/12/15 (Com’l)
5
5 Page 
VANTIS
CAPACITANCE (Note 1)
Parameter
Symbol
Parameter Description
CIN
COUT
Input Capacitance
Output Capacitance
VIN = VCC –0.5 V
VOUT = 2.0 V
Test Conditions
VCC = 5.0 V, TA = 25°C
f = 1 MHz
Typ Unit
6 pF
8 pF
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2)
Parameter
Symbol
Parameter Description
tPD Input, I/O, or Feedback to Combinatorial Output
tS
Setup Time from Input, I/O, or Feedback to
Clock
D-type
T-type
tH
tCO
tWL
tWH
fMAX
Register Data Hold Time
Clock to Output
Clock Width
LOW
HIGH
External Feedback 1/(tS + tCO)
Maximum
Frequency Internal Feedback (fCNT)
D-type
T-type
D-type
T-type
No Feedback
tSL
tHL
tGO
tGWL
tPDL
Setup Time from Input, I/O, or Feedback to Gate
Latch Data Hold Time
Gate to Output
Gate Width LOW
Input, I/O, or Feedback to Output Through Transparent
Input or Output Latch
tSIR Input Register Setup Time
tHIR Input Register Hold Time
tICO Input Register Clock to Combinatorial Output
D-type
tICS Input Register Clock to output Register Setup
T-type
tWICL
tWICH
fMAXIR
tSIL
tHIL
tIGO
tIGOL
Input Register
Clock Width
LOW
HIGH
Maximum Input Register Frequency
Input Latch Setup Time
Input Latch Hold Time
Input Latch Gate to Combinatorial Output
Input Latch Gate to Output Through Transparent
Output Latch
-6 -7 -10 -12 -15
Min Max Min Max Min Max Min Max Min Max Unit
6 7.5 10 12 15 ns
5 5.5 6.5
7 10 ns
6 6.5 7.5
8 11 ns
00
0
0 0 ns
4 5 6.5 8 10 ns
2.5 3
4
6 6 ns
2.5 3
4
6 6 ns
111 95 77 66.7 50 MHz
100 87 72 62.5 47.6 MHz
166 133 100 76.9 66.6 MHz
150 125 91 71.4 62.5 MHz
200 166.7
125
83.3 83.3 MHz
5 5.5 6.5
7 10 ns
00
0
0 0 ns
5 6 7.5 8.5 11 ns
23
4
6 6 ns
9 9.5 14 14.5 17 ns
1.5 2
2
2 2 ns
1.5 2
2.5
2.5 2.5
ns
10 11 15.5 16 18 ns
8 9 11 12 15 ns
9 10 12
13 16 ns
2.5 3
4
6 6 ns
2.5 3
4
6 6 ns
200 166.7
125
83.3 83.3 MHz
1.5 2
2
2.5 2.5
ns
1.5 2
2.5
3 3 ns
11 12
17 17 20 ns
13 14
18 19.5 22 ns
MACH231-6/7/10/12/15 (Com’l)
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MACH231-15.PDF ] | |
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