PDF NCN5193 Data sheet ( Hoja de datos )

Número de pieza	NCN5193
Descripción	HART Modem
Fabricantes	ON Semiconductor
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No Preview Available ! NCN5193 HART Modem Description The NCN5193 is a single−chip, CMOS modem for use in highway addressable remote transducer (HART) field instruments and masters. The modem and a few external passive components provide all of the functions needed to satisfy HART physical layer requirements including modulation, demodulation, receive filtering, carrier detect, and transmit−signal shaping. In addition, the NCN5193 also has an integrated DAC for low-BOM current loop slave transmitter implementation. The NCN5193 uses phase continuous frequency shift keying (FSK) at 1200 bits per second. To conserve power the receive circuits are disabled during transmit operations and vice versa. This provides the half−duplex operation used in HART communications. Features • Single−chip, Half−duplex 1200 Bits per Second FSK Modem • Bell 202 Shift Frequencies of 1200 Hz and 2200 Hz • 1.8 V − 3.5 V Power Supply • Transmit−signal Wave Shaping • Receive Band−pass Filter • Low Power: Optimal for Intrinsically Safe Applications • Compatible with 1.8 V or 3.3 V Microcontroller • Internal Oscillator Requires 460.8 kHz, 920 kHz, 1.84 MHz or 3.68 MHz Crystal or Ceramic Resonator • SPI Communication • Integrated 17 bit Sigma-Delta DAC • Meets HART Physical Layer Requirements • Industrial Temperature Range of −40°C to +85°C • Available in 32−pin NQFP Package • These are Pb−Free Devices Applications • HART Multiplexers • HART Modem Interfaces • 4 − 20 mA Loop Powered Transmitters www.onsemi.com MARKING DIAGRAM 1 32 QFN32 CASE 488AM 1 NCN 5193 AWLYYWWG G NCN5193 = Specific Device Code A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 13 of this data sheet. © Semiconductor Components Industries, LLC, 2016 September, 2016 − Rev. 3 1 Publication Order Number: NCN5193/D 1 page NCN5193 VDDA 1.8 V − 3.5 V R11 R12 R10 RESET VPOR KICK μC RxD CD TxD RTS CS DATA SCLK 3.6864 MHz CLK1 CLK2 XOUT XIN C7 C8 XT1 TYPICAL APPLICATION C4 R6 C6 C5 VDD VDDA RxAFI RxAF RxAN RxAP R7 R5 R8 R9 R3 C3 C2 C1 HART IN R4 R2 R1 NCN5193 CBIAS R13 VSS MODE AREF R14 R15 CDREF R VDDA 16 U2 TxA DAC JUMP DACREF TEST2 TEST1 S VDDA HART & 4 – 20 mA OUT U1 Figure 2. Application Diagram NCN5193 Table 7. TYPICAL BILL OF MATERIALS Reference Designator Value (Typical) U1 − U2 − R1, R2 1.5M R3, R5 806k R4 1.3M R6 174k R7 2.2M R8, R9 422k R11 240k R12, R15, R10 200k R13 120k R14, R16 14k7 C1 1 nF C2 470 pF C3 200 pF C4 220 pF C5 20 pF C6 330 pF C7, C8 18 pF XT1 3.6864 MHz Tolerance − − 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 5% 5% 5% 5% 5% 5% 10% 100 ppm Manufacturer ON Semiconductor ON Semiconductor Raltron Part Number NCN5193 LM285 AS−3.6864−18 www.onsemi.com 5 5 Page NCN5193 VDD VPOR POR AREF OPA CS SCLK DATA b7 b6 b5 b4 b3 b2 b1 b0 Figure 14. SPI Frame KVDE 20110408 .1 Figure 13. Power on Reset Block Byte 0 76543210 0 1 0 Address 0 Byte 1 76543210 W15−W8 for Reg 1, 2, 3 76543210 W23−W16 for Reg A Byte 2 76543210 W7−W0 for Reg 1, 2, 3 76543210 W15−W8 for Reg A Byte 3 76543210 W7−W0 for Reg A Figure 15. Register Write Format SPI Communication The SPI bus on the NCN5193 is made up of three signals; DATA, SCLK, and CS operating in SPI mode 1 (CPOL = 0, CPHA = 1, as shown in Figure 14). CS should first go high at least one clock cycle before the other signals change. One clock cycle is 2.17 ms at a master clock frequency of 460.8 kHz. SCLK can begin to clock in DATA serially to the chip on the falling edge of SCLK. SCLK should have a maximum frequency of 460.8 kHz. The format of the data should be most significant bit first. DATA is shifted into the chip on the falling edge of SCLK, and thus for correct operation DATA should change only on the rising edge of SCLK. The first bit shifted in is the MSB. Once the data is shifted in, CS should go low no sooner than one clock cycle after the last rising edge of the last byte of SCLK. To write to a register, first a command byte must be sent which includes the register address (as shown in Figure 15), followed by 2 bytes (for GCR, CCR, and ACR) or 3 bytes (for SDR) of data. When writing data to the GCR, CCR, or ACR registers, the first byte must be the bitwise inverse of the configuration data in the second byte. Internal Registers The NCN5193 has four registers to setup its internal operation. In Tables 10 to 16 an explanation of their usage is given, together with their reset values. Table 10. GENERAL CONFIGURATION REGISTER (GCR) Address Bit 7 Bit 6 Bit 5 Bit 4 0x01 Reset 1 0 0 0 Data - - - RXD_IDLE Bit 3 0 - Bit 2 1 WDT_CLK Bit 1 Bit 0 01 WDT_KICK The general configuration register is used to set the RxD idle state, enable or disable the monitoring of the system clock and setting the watchdog timer kick source. A write to this register should always be preceded with an inverted value to the shadow register. Table 11. GENERAL CONFIGURATION REGISTER PARAMETERS Parameter Value Description RXD_IDLE 0 Low Sets the idle state for the RxD pin (when CD is low) 1 High WDT_CLK 0 Enable Disable/Enable monitoring of the clock frequency by the watchdog timer. 1 Disable WDT_KICK 00 Disable Kick signal to watchdog timer is disabled 01 External Watchdog kick source is a pulse on the KICK pin 10 Sigma-Delta Watchdog kick source is an write to the Sigma-Delta Data register (SDR) 11 Info www.onsemi.com 11 11 Page

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