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PDF AD5681R Datasheet ( Hoja de datos )

Número de pieza AD5681R
Descripción Tiny 16-/14-/12-Bit SPI nanoDAC+
Fabricantes Analog Devices 
Logotipo Analog Devices Logotipo

Total 28 Páginas
		
AD5681R Hoja de datos, Descripción, Manual
Data Sheet
Tiny 16-/14-/12-Bit SPI nanoDAC+, with
±2 (16-Bit) LSB INL and 2 ppm/°C Reference
AD5683R/AD5682R/AD5681R/AD5683
FEATURES
Ultrasmall package: 2 mm × 2 mm, 8-lead LFCSP
High relative accuracy (INL): ±2 LSB maximum at 16 bits
AD5683R/AD5682R/AD5681R
Low drift, 2.5 V reference: 2 ppm/°C typical
Selectable span output: 2.5 V or 5 V
AD5683
External reference only
Selectable span output: VREF or 2 × VREF
Total unadjusted error (TUE): 0.06% of FSR maximum
Offset error: ±1.5 mV maximum
Gain error: ±0.05% of FSR maximum
Low glitch: 0.1 nV-sec
High drive capability: 20 mA
Low power: 1.2 mW at 3.3 V
Independent logic supply: 1.8 V logic compatible
Wide operating temperature range: −40°C to +105°C
Robust 4 kV HBM ESD protection
APPLICATIONS
Process controls
Data acquisition systems
Digital gain and offset adjustment
Programmable voltage sources
GENERAL DESCRIPTION
The AD5683R/AD5682R/AD5681R/AD5683, members of the
nanoDAC+® family, are low power, single-channel, 16-/14-/12-bit
buffered voltage out digital-to-analog converters (DACs). The
devices, except the AD5683, include an enabled by default internal
2.5 V reference, offering 2 ppm/°C drift. The output span can be
programmed to be 0 V to VREF or 0 V to 2 × VREF. All devices
operate from a single 2.7 V to 5.5 V supply and are guaranteed
monotonic by design. The devices are available in a 2.00 mm ×
2.00 mm, 8-lead LFCSP or a 10-lead MSOP.
The internal power-on reset circuit ensures that the DAC register
is written to zero scale at power-up while the internal output
buffer is configured in normal mode. The
AD5683R/AD5682R/AD5681R/AD5683 contain a power-down
mode that reduces the current consumption of the device to 2 µA
(maximum) at 5 V and provides software selectable output loads
while in power-down mode.
The AD5683R/AD5682R/AD5681R/AD5683 use a versatile
3-wire serial interface that operates at clock rates of up to 50 MHz.
Some devices also include asynchronous RESET pin and VLOGIC
pin options, allowing 1.8 V compatibility.
Rev. C
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
LDAC
RESET
FUNCTIONAL BLOCK DIAGRAM
VLOGIC*
VREF
VDD
POWER-ON
RESET
DAC
REGISTER
2.5V
REF
REF
16-/14-/12-BIT
DAC
AD5683R/
AD5682R/
AD5681R
OUTPUT
BUFFER
VOUT
INPUT
CONTROL LOGIC
POWER-DOWN
CONTROL LOGIC
RESISTOR
NETWORK
*NOT AVAILABLE IN ALL THE MODELS
SYNC SCLK SDI SDO*
GND
Figure 1. AD5683R/AD5682R/AD5681R MSOP
(For more information, see the Functional Block Diagrams—LFCSP section.)
Table 1. Single-Channel nanoDAC+ Portfolio
Interface Reference 16-Bit
14-Bit
SPI
Internal
AD5683R AD5682R
External
AD5683
I2C
Internal
AD5693R AD5692R
External
AD5693
12-Bit
AD5681R
AD5691R
PRODUCT HIGHLIGHTS
1. High Relative Accuracy (INL).
AD5683R/AD5683 (16-bit): ±2 LSB maximum.
2. Low Drift, 2.5 V On-Chip Reference.
2 ppm/°C typical temperature coefficient.
5 ppm/°C maximum temperature coefficient.
3. Two Package Options.
2.00 mm × 2.00 mm, 8-lead LFCSP.
10-lead MSOP.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2013–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com

1 page

AD5681R pdf
Data Sheet
AD5683R/AD5682R/AD5681R/AD5683
Parameter
REFERENCE OUTPUT
Output Voltage
Voltage Reference TC3
A-Grade
B-Grade
Output Impedance
Output Voltage Noise
Output Voltage Noise Density
Capacitive Load Stability
Load Regulation Sourcing
Load Regulation Sinking
Output Current Load Capability
Line Regulation
Thermal Hysteresis
REFERENCE INPUT
Reference Current
Reference Input Range
Reference Input Impedance
LOGIC INPUTS
IIN, Input Current
VINL, Input Low Voltage4
VINH, Input High Voltage4
CIN, Pin Capacitance
LOGIC OUTPUTS (SDO)5
Output Low Voltage, VOL
Output High Voltage, VOH
Pin Capacitance
POWER REQUIREMENTS
VLOGIC5
ILOGIC5
VDD
IDD6
Normal Mode7
Power-Down Modes8
Min Typ Max Unit Test Conditions/Comments
2.4975
2.5025
5 20
25
0.05
16.5
250
5
50
30
±5
80
125
25
V
ppm/°C
ppm/°C
µV p-p
nV/√Hz
µF
µV/mA
µV/mA
mA
µV/V
ppm
ppm
At ambient
See the Terminology section
0.1 Hz to 10 Hz
At ambient; f = 10 kHz, CL = 10 nF
RL = 2 kΩ
At ambient; VDD ≥ 3 V
At ambient
VDD ≥ 3 V
At ambient
First cycle
Additional cycles
26 µA VREF = VDD = VLOGIC = 5 V, gain = 1
47 µA VREF = VDD = VLOGIC = 5 V, gain = 2
1 VDD V
120 kΩ Gain = 1
60 kΩ Gain = 2
0.7 × VDD
2
±1
0.3 × VDD
µA
V
V
pF
Per pin
VDD − 0.4
4
0.4
V
V
pF
ISINK = 200 μA
ISOURCE = 200 μA
1.8 − 10%
5 + 10% V
0.25 3
µA
2.7 5.5 V
VREF + 1.5
5.5 V
350 500
110 180
2
µA
µA
µA
VIH = VLOGIC or VIL = GND
Gain = 1
Gain = 2
VIH = VDD, VIL = GND
Internal reference enabled
Internal reference disabled
1 Linearity is calculated using a reduced code range: AD5683R and AD5683 (Code 512 to Code 65,535); AD5682R (Code 128 to Code 16,384); AD5681R (Code 32 to
Code 4096). Output unloaded.
2 When drawing a load current at either rail, the output voltage headroom, with respect to that rail, is limited by the 20 Ω typical channel resistance of the output
devices; for example, when sinking 1 mA, the minimum output voltage = 20 Ω, 1 mA generates 20 mV. See Figure 38 (Headroom/Footroom vs. Load Current).
3 Reference temperature coefficient is calculated as per the box method. See the Terminology section for more information.
4 Substitute VLOGIC for VDD if device includes a VLOGIC pin.
5 The VLOGIC and SDO pins are not available on all models.
6 If the VLOGIC pin is not available, IDD = IDD + ILOGIC.
7 Interface inactive. DAC active. DAC output unloaded.
8 DAC powered down.
Rev. C | Page 5 of 28

5 Page

AD5681R arduino
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
2
VDD = 5V
TA = 25°C
VREF = 2.5V
1
0
–1
–2
0 10000 20000 30000 40000 50000 60000 65535
CODE
Figure 11. AD5683R/AD5683 INL
2
VDD = 5V
TA = 25°C
VREF = 2.5V
1
0
–1
–2
0 2000 4000 6000 8000 10000 12000 14000 16383
CODE
Figure 12. AD5682R INL
2.0
VDD = 5V
1.5
TA = 25°C
VREF = 2.5V
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
0
500 1000 1500 2000 2500 3000 3500 4000
CODE
Figure 13. AD5681R INL
AD5683R/AD5682R/AD5681R/AD5683
2
VDD = 5V
TA = 25°C
VREF = 2.5V
1
0
–1
–2
0
10000
20000
30000 40000
CODE
50000
60000 65535
Figure 14. AD5683R/AD5683 DNL
1.0
VDD = 5V
0.8 TA = 25°C
VREF = 2.5V
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0
2000 4000 6000 8000 10000 12000 14000 16383
CODE
Figure 15. AD5682R DNL
1.0
VDD = 5V
0.8 TA = 25°C
VREF = 2.5V
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0
500 1000 1500 2000 2500 3000 3500 4000
CODE
Figure 16. AD5681R DNL
Rev. C | Page 11 of 28

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