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PDF CLC030 Data sheet ( Hoja de datos )
| Número de pieza | CLC030 | |
| Descripción | SMPTE 292M/259M Digital Video Serializer with Video and Ancilliary Data FIFOs and Integrated Cable Driver | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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PRELIMINARY
February 2002
CLC030
SMPTE 292M/259M Digital Video Serializer with Video
and Ancilliary Data FIFOs and Integrated Cable Driver
General Description
The CLC030 SMPTE 292M/259M Digital Video Serializer
with Ancilliary Data FIFO and Integrated Cable Driver is a
monolithic integrated circuit that encodes, serializes and
transmits bit-parallel digital video data conforming to SMPTE
125M and 267M standard definition, 10-bit wide component
video and SMPTE 260M, 274M, 295M and 296M high-
definition, 20-bit wide component video standards. The
CLC030 operates at SMPTE 259M serial data rates of
270 Mbps, 360 Mbps, the SMPTE 344M (proposed) serial
data rate of 540 Mbps; and the SMPTE 292M serial data
rates of 1483.5 and 1.485 Gbps. The serial data clock fre-
quency is internally generated and requires no external fre-
quency setting, trimming or filtering components*.
Functions performed by the CLC030 include: parallel-to-
serial data conversion, SMPTE standard data encoding,
NRZ to NRZI data format conversion, serial data clock gen-
eration and encoding with the serial data, automatic video
rate and format detection, ancilliary data packet storage,
manipulation and insertion, and serial data output driving.
The CLC030 has circuitry for automatic EDH/CRC character
and flag generation and insertion per SMPTE RP-165 (stan-
dard definition) or SMPTE 292M (high definition). Optional
LSB dithering is implemented which prevents pathological
pattern generation. Unique to the CLC030 are its video and
ancilliary data FIFOs. The video FIFO allows from 0 to 4
parallel data clock delays to be inserted in the data path for
video timing purposes. The ancilliary data port and on-chip
FIFO and control circuitry offer elegant handling and inser-
tion of ancilliary data packets and checksums in the ancilliary
data space. The CLC030 also has an exclusive built-in self-
test (BIST) and video test pattern generator (TPG) with SD
and HD component video test patterns: reference black, PLL
and EQ pathologicals and colour bars in 4:3 and 16:9 raster
formats for NTSC and PAL standards*. The colour bar pat-
terns feature optional bandwidth limiting coding in the
chroma and luma transitions.
The CLC030 has a unique multi-function I/O port which
provides access to control and configuration signals and
data. This port may be programmed to provide external
access to control functions and data for use as inputs and
outputs. This allows the designer greater flexibility in tailoring
the CLC030 to the desired application. At power-up or after a
reset command, the CLC030 is auto-configured to a default
operating condition. Separate power pins for the output
driver, PLL and the serializer improve power supply rejec-
tion, output jitter and noise performance.
The CLC030’s internal circuitry is powered from +2.5V and
the I/O circuitry from a +3.3V supply. Power dissipation is
typically 430mW at 1.485Gbps including two 75Ω AC-
coupled and back-matched output loads. The device is pack-
aged in a 64-pin TQFP.
Features
n SDTV/HDTV serial digital video standard compliant
n Supports 270 Mbps, 360 Mbps, 540 Mbps, 1.4835Gbps
and 1.485 Gbps SDV data rates with auto-detection
n LSB dithering option
n No external serial data rate setting or VCO filtering
components required*
n Fast PLL lock time: < 150µs typical at 1.485 Gbps
n Adjustable depth video FIFO for timing alignment
n Built-in self-test (BIST) and video test pattern generator
(TPG)*
n Automatic EDH/CRC word and flag generation and
insertion
n On-chip ancilliary data FIFO and insertion control
circuitry
n Flexible control and configuration I/O port
n LVCMOS compatible data and control inputs and
outputs
n 75Ω ECL-compatible, differential, serial cable-driver
outputs
n 3.3V I/O power supply, 2.5V logic power supply
operation
n Low power: typically 430mW
n 64-pin TQFP package
n Commercial temperature range 0˚C to +70˚C
* Patent applications made or pending.
Applications
n SDTV/HDTV parallel-to-serial digital video interfaces for:
— Video cameras
— VTRs
— Telecines
— Digital video routers and switchers
— Digital video processing and editing equipment
— Video test pattern generators and digital video test
equipment
— Video signal generators
Order Number CLC030VEC
64-Pin TQFP
NS Package Number
VEC-64A
© 2002 National Semiconductor Corporation DS200003
www.national.com
1 page  
Absolute Maximum Ratings (Note 1)
It is anticipated that this device will not be offered in
a military qualified version. If Military/Aerospace speci-
fied devices are required, please contact the National
Semiconductor Sales Office / Distributors for availability
and specifications.
CMOS I/O Supply Voltage
(VDDIO– VSSIO):
SDO Supply Voltage
(VDDSD– VSSSD):
Digital Logic Supply Voltage
(VDDD– VSSD):
PLL Supply Voltage
(VDDPLL– VSSPLL):
CMOS Input Voltage
(Vi):
CMOS Output Voltage
(Vo):
4.0V
4.0V
3.0V
3.0V
VSSIO −0.15V to
VDDIO +0.15V
VSSIO −0.15V to
VDDIO +0.15V
CMOS Input Current (single input):
Vi = VSSIO −0.15V:
Vi = VDDIO +0.15V:
CMOS Output Source/Sink Current:
SDO Output Sink Current:
Package Thermal Resistance
θJA @ 0 LFM Airflow
θJA @ 500 LFM Airflow
θJC
Storage Temp. Range:
Junction Temperature:
Lead Temperature (Soldering 4 Sec):
ESD Rating (HBM):
ESD Rating (MM):
−5 mA
+5 mA
±10 mA
40 mA
47˚C/W
27˚C/W
6.5˚C/W
−65˚C to +150˚C
+150˚C
+260˚C
2 kV
250V
Recommended Operating Conditions
Symbol
VDDIO
VDDSD
VDDD
VDDPLL
VIL
VIH
TA
tJIT
Parameter
CMOS I/O Supply
Voltage
SDO Supply Voltage
Digital Logic Supply
Voltage
PLL Supply Voltage
CMOS Input Voltage,
Low Level
CMOS Input Voltage
High Level
Operating Free Air
Temperature
Video Clock Jitter
Conditions
VDDIO−VSSIO
VDDSD−VSSSD
VDDD– VSSD
VDDPLL– VSSPLL
Reference
Min Typ
3.150 3.300
3.150 3.300
2.375 2.500
2.375 2.500
VSSIO
VCLK
0
100
Max
3.450
3.450
2.625
2.625
VDDIO
+70
Units
V
V
V
V
V
V
˚C
psP-P
DC Electrical Characteristics
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (Notes 2, 3).
Symbol
Parameter
Conditions
Reference
Min Typ
VIH
VIL
IIH
IIL
VOH
Input Voltage High Level
Input Voltage Low Level
Input Current High Level
Input Current Low Level
CMOS Output Voltage
High Level
VIH = VDDIO
VIL = VSSIO
IOH = −6.6 mA
All LVCMOS
Inputs
All LVCMOS
Outputs
2.0
VSSIO
+90
−1
2.4 2.7
VOL
CMOS Output Voltage
IOL = +6.6 mA
Low Level
VSSIO
VSSIO
+0.3
VSDO
Serial Driver Output
Voltage
Test Circuit, Test Loads
Shall Apply
SDO, SDO
720 800
IDD
(3.3V)
Power Supply Current,
3.3V Supply, Total
VCLK = 27 MHz, NTSC
Colour Bar Pattern, Test
Circuit, Test Loads Shall
Apply
VDDIO, VDDSD
48
IDD
(3.3V)
Power Supply Current,
3.3V Supply, Total
VCLK = 74.25 MHz, NTSC
Colour Bar Pattern, Test
Circuit, Test Loads Shall
Apply
VDDIO, VDDSD
66
5
Max
VDDIO
0.8
+150
−20
VDDIO
VSSIO
+0.5V
880
65
Units
V
V
µA
µA
V
V
mVP-P
mA
90 mA
www.national.com
5 Page 
Device Operation (Continued)
FIGURE 1. Control Data Read Timing (2 read and 1 write cycle shown)
DS200003-9
FIGURE 2. Control Data Write Timing
DS200003-10
Ancilliary Data Functions
The CLC030 can insert Ancilliary Data into the serial data
stream. This ancilliary data and related control characters
are defined in the relevant SMPTE standards and may re-
side in the horizontal and vertical blanking intervals. The
data can consist of different types of message packets in-
cluding audio data. The serial ancilliary data space must be
formatted according to SMPTE 291M. The CLC030 supports
ancilliary data in the chrominance channel (C’r/C’b) only for
high-definition operation. Ancilliary data for standard defini-
tion follows the requirements of SMPTE 125M.
Figure 3 shows the sequence of clock, data and control
signals for writing ancilliary data to the port. In ancilliary data
write mode, 10-bit Ancilliary Data is written into the port
using bits AD[9:0] and routed to the ancilliary data FIFO.
From the FIFO, the ancilliary data can be written into the
ancilliary data spaces in the serial video data stream. Ancil-
liary data write mode is invoked by making the ANC/CTRL
input high and the RD/WR input low. Data presented to the
port on a falling edge of ACLK is written into the FIFO on the
next rising edge of ACLK. Ancilliary data may only be written
to the FIFO when in the ancilliary data mode. Ancilliary data
cannot be read from the port.
Admission of ancilliary data to and insertion into the video
data stream from the FIFO is controlled by a system of
masking and control bits in the control registers. The details
and functions of these control registers and bits is explained
later in this datasheet.
11 www.national.com
11 Page | ||
| Páginas | Total 29 Páginas | |
| PDF Descargar | [ Datasheet CLC030.PDF ] | |
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