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PDF CLC021 Data sheet ( Hoja de datos )
| Número de pieza | CLC021 | |
| Descripción | SMPTE 259M Digital Video Serializer with EDH Generation and Insertion | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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July 2003
CLC021
SMPTE 259M Digital Video Serializer with EDH
Generation and Insertion
General Description
The CLC021 SMPTE 259M Digital Video Serializer with EDH
Generation and Insertion is a monolithic integrated circuit
that encodes, serializes and transmits bit-parallel digital data
conforming to SMPTE 125M and 267M component video
and SMPTE 244M composite video standards. The CLC021
can also serialize other 8- or 10-bit parallel data. The
CLC021 operates at data rates from below 100 Mbps to over
400 Mbps. The serial data clock frequency is internally gen-
erated and requires no external frequency setting, trimming
or filtering components*.
Functions performed by the CLC021 include: parallel-to-
serial data conversion, ITU-R BT.601-4 input data clipping,
data encoding using the SMPTE polynomial (X9+X4+1), data
format conversion from NRZ to NRZI, parallel data clock
frequency multiplication and encoding with the serial data,
and differential, serial output data driving. The CLC021 has
circuitry for automatic EDH character and flag generation
and insertion per SMPTE RP-165. The CLC021 has an
exclusive built-in self-test (BIST) and video test pattern gen-
erator (TPG) with 16 component video test patterns: refer-
ence black, PLL and EQ pathologicals and modified colour
bars in 4:3 and 16:9 raster formats for NTSC and PAL
formats*.
The CLC021 has inputs for enabling sync detection, non-
SMPTE mode operation, enabling the EDH function, NRZ/
NRZI mode control and an external reset control. Outputs
are provided for H, V and F bits, new TRS sync character
position indication, ancilliary data header detection, NTSC/
PAL raster indication and PLL lock detect. Separate power
pins for the output driver, VCO and the serializer improve
power supply rejection, output jitter and noise performance.
The CLC021AVGZ-5.0V is powered by a single +5V supply.
The CLC021AVGZ-3.3V is powered by a single +3.3V sup-
ply. Power dissipation is typically 235 mW including two 75Ω
back-matched output loads. The device is packaged in a
JEDEC metric 44-lead PQFP.
Features
n SMPTE 259M serial digital video standard compliant
n Supports all NTSC and PAL standard component and
composite serial video data rates
n No external serial data rate setting or VCO filtering
components required*
n Fast VCO lock time: <75 µs at 270 Mbps
n Built-in self-test (BIST) and video test pattern generator
(TPG) with 16 internal patterns*
n Automatic EDH character and flag generation and
insertion per SMPTE RP 165
n Non-SMPTE mode operation as parallel-to-serial
converter
n NRZ-to-NRZI conversion control
n HCMOS/LSTTL-compatible data and control inputs and
outputs for CLC021AVGZ-5.0, LVCMOS for
CLC021AVGZ-3.3
n 75Ω ECL-compatible, differential, serial cable-driver
outputs
n Single power supply operation: 5V (CLC021AVGZ-5.0)
or 3.3V (CLC021AVGZ-3.3) in TTL or ECL systems
n Low power: typically 235 mW
n JEDEC 44-lead metric PQFP package
n Commercial temperature range 0˚C to +70˚C
* Patents applications made or pending.
Applications
n SMPTE 259M parallel-to-serial digital video interfaces
for:
— Video cameras
— VTRs
— Telecines
— Video test pattern generators and digital video test
equipment
— Video signal generators
n Non-SMPTE video applications
n Other high data rate parallel/serial video and data
applications
Typical Application
© 2003 National Semiconductor Corporation DS101368
10136812
www.national.com
1 page  
DC Electrical Characteristics—CLC021AVGZ-3.3 (Continued)
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (Notes 2, 3).
Symbol
Parameter
Conditions
Reference
Min Typ
VOH
CMOS Output Voltage
IOH = −8 mA
High Level
VOL
CMOS Output Voltage
IOL = +8 mA
Low Level
All CMOS
Outputs
2.4 3.0
0.0 0.3
VSDO
Serial Driver Output
Voltage
RL = 75Ω 1%,
RREF = 1.69 kΩ 1%,
Figure 2
SDO, SDO
720 800
IDD
Power Supply Current,
RL = 75Ω 1%,
Total
RREF = 1.69 kΩ 1%,
PCLK = 27 MHz, NTSC
Colour Bar Pattern,
Figure 2
33
Max
VDD
VSS + 0.5V
880
55
Units
V
V
mVP-P
mA
AC Electrical Characteristics—CLC021AVGZ-5.0
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (Note 3).
Symbol
Parameter
Conditions
Reference
Min
BRSDO
FPCLK
Serial Data Rate
Reference Clock
Input Frequency
(Note 5)
SDO, SDO
PCLK
100
10
Reference Clock Duty
Cycle
PCLK
45
tr, tf Rise Time, Fall Time
DN, PCLK
tj
Serial Output Jitter
270 Mbps,Figure 2, (Note 6)
tjit
Serial Output Jitter
(Notes 4, 5)
tr, tf Rise Time, Fall Time 20%–80%, (Notes 4, 5)
SDO, SDO
Output Overshoot
(Note 4)
1.0
500
tLOCK
tSU
tHLD
LGEN
RGEN
Lock Time
Setup Time
Hold Time
Output Inductance
Output Resistance
(Notes 5, 7)
Figure 3 (Note 4)
Figure 3 (Note 4)
(Note 4)
(Note 4)
DN to PCLK
DN from PCLK
SDO, SDO
3
3
Typ
50
1.5
220
100
800
1
75
2
2
6
25k
AC Electrical Characteristics—CLC021AVGZ-3.3
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (Note 3).
Symbol
Parameter
Conditions
Reference
Min
BRSDO
FPCLK
Serial Data Rate
Reference Clock
Input Frequency
(Note 5)
SDO, SDO
PCLK
100
10
Reference Clock Duty
Cycle
PCLK
45
tr, tf Rise Time, Fall Time
DN, PCLK
tj
Serial Output Jitter
270 Mbps,Figure 2, (Note 6)
tjit
Serial Output Jitter
(Notes 4, 5)
tr, tf Rise Time, Fall Time 20%–80%, (Notes 4, 5)
SDO, SDO
Output Overshoot
(Note 4)
1.0
500
tLOCK
tSU
tHLD
Lock Time
Setup Time
Hold Time
(Notes 5, 7)
Figure 3 (Note 4)
Figure 3 (Note 4)
DN to PCLK
DN from PCLK
4
4
Typ
50
1.5
220
100
800
1
75
2
2
Max
400
40
55
3.0
200
1500
Max
400
40
55
3.0
200
1500
Units
Mbps
MHz
%
ns
psP-P
psP-P
ps
%
µs
ns
ns
nH
Ω
Units
Mbps
MHz
%
ns
psP-P
psP-P
ps
%
µs
ns
ns
5 www.national.com
5 Page 
Device Operation (Continued)
FIGURE 6. Built-In Self-Test Control Sequence
10136806
TEST PATTERN GENERATOR
The CLC021 includes an on-board test pattern generator
(TPG). Four full-field component video test patterns for both
NTSC and PAL standards, and 4x3 and 16x9 raster sizes are
produced. The test patterns are: flat-field black, PLL patho-
logical, equalizer (EQ) pathological and a modified 75%,
8-colour vertical bar pattern. The pathologicals follow recom-
mendations contained in SMPTE RP 178–1996 regarding
the test data used. The colour bar pattern does not incorpo-
rate bandwidth limiting coding in the chroma and luma data
when transitioning between the bars. For this reason, it may
not be suitable for use as a visual test pattern or for input to
video D-to-A conversion devices unless measures are taken
to restrict the production of out-of-band frequency compo-
nents.
The TPG is operated by applying the code for the desired
test pattern to D0 through D3 (D4 through D9 are 00h). Since
all parallel data inputs are equipped with internal pull-down
devices, only those inputs D0 through D3 which require a
logic-1 need be pulled high. Next, apply a 27 MHz or 36 MHz
signal, appropriate to the raster size desired, at the PCLK
input and wait until the Lock_Detect output goes true indi-
cating the VCO is locked on frequency. Then, take
TPG_Enable, pin 29, to a logic high. The serial test pattern
data appears on the SDO outputs. The Lock_Detect output
may be temporarily connected to TPG_Enable to automate
TPG operation. The TPG mode is exited by taking TPG_En-
able to a logic low. Table 1 gives device pin functions for this
mode. Table 2 gives the available test patterns and selection
codes.
FIGURE 7. Test Pattern Generator Control Sequence
11
10136807
www.national.com
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet CLC021.PDF ] | |
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