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PDF CLC011 Data sheet ( Hoja de datos )

Número de pieza CLC011
Descripción Serial Digital Video Decoder
Fabricantes National Semiconductor 
Logotipo National Semiconductor Logotipo



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January 1999
CLC011
Serial Digital Video Decoder
General Description
National’s Comlinear CLC011, Serial Digital Video Decoder,
decodes and descrambles SMPTE 259M standard Serial
Digital Video datastreams with serial clock into 10-bit parallel
words and a corresponding word-rate clock. SMPTE 259M
standard parallel data is encoded and scrambled using a
9-bit shift register and is also converted from NRZ to NRZI.
The CLC011 restores the original parallel data by reversing
the encoding process. The CLC011 also extracts timing in-
formation embedded in the SDV data. These reserved code
words, known as Timing Reference Signals (TRS), indicate
the start and end of each active video line. By decoding the
TRS, the CLC011 correctly identifies the word boundaries of
the encoded input data. Detection of the TRS reserved
codes is indicated by low-true signals at the TRS and End of
Active Video (EAV) outputs.
The CLC011’s design using current-mode logic (CML) re-
duces noise injection into the power supply thereby easing
board layout and interfacing. The CMOS compatible outputs,
which feature controlled rise and fall times, may be set for ei-
ther 3.3V or 5V swings with the VDP and VCP inputs.
The CLC011 Serial Digital Video Decoder, CLC014 Adaptive
Cable Equalizer and the CLC016 Data Retiming PLL com-
bine to provide a complete Serial Digital Video receiver sys-
tem.
The CLC011 is packaged in a 28-pin PLCC.
Features
n Data decoding and deserializing
n CLC011B operates to 360Mbps
n CLC011A operates to 300Mbps
n Low noise injection to power supplies
n Single +5V or −5.2V supply operation
n Output levels programmable for interface to 5V or 3.3V
logic
n Low power
n Low cost
Block Diagram
© 1999 National Semiconductor Corporation DS100086
DS100086-1
www.national.com

1 page




CLC011 pdf
Overview
The CLC011, Serial Digital Video Decoder, decodes and de-
scrambles SMPTE 259M standard Serial Digital Video
datastreams into 10-bit parallel words and a corresponding
word-rate clock. The following information describes:
the CLC011 operation,
recommended interface circuitry, and
PCB layout suggestions.
Applications assistance for the CLC011 may be obtained by
calling the Interface Applications Hotline, (408) 721-8500.
Input Interfacing — Signal Inputs
The serial data and clock inputs of the CLC011 are both dif-
ferential. Their input voltage ranges from 2.5V above the
negative supply (VEE +2.5V) to the positive supply voltage
(VCC). Supply voltages for the CLC011 may be either +5V or
–5.2V for ECL compatibility and interfacing. When operated
from the negative supply, inputs accept standard ECL signal
levels. The minimum differential input swing is 200 mV. The
CLC011 interfaces with the CLC016 Data Retiming PLL as
shown in Figure 2. A simplified schematic of the CLC011’s
signal inputs appears in Figure 3.
DS100086-5
FIGURE 3. Simplified Input Buffer Schematic
Input Interfacing — Control Inputs
Three TTL-compatible inputs control operation of the
CLC011: NRZI, DESC and FE. A typical interface circuit for
the control inputs is shown in Figure 4.
FIGURE 2. Interface with CLC016
DS100086-4
DS100086-6
FIGURE 4. Typical Control Logic Connection
NRZI: NRZI, when a logic high, enables NRZI to NRZ con-
version. For standard SMPTE 259M operation, NRZI is high.
DESC (Descramble): The bits of a SMPTE 259M
datastream are scrambled upon encoding according to a
polynomial equation. DESC, when a logic high, enables de-
scrambling of the encoded signal. For standard SMPTE
259M operation, DESC is high.
FE (Framing Enable): SMPTE 259M datastreams include a
four-word-long reserved sequence known as the Timing Ref-
erence Signal (TRS). Using this sequence, the CLC011 de-
termines the position of word boundaries, also known as
framing, of the incoming data.
The FE input, when a logic high and following recognition of
a TRS, causes the CLC011 to automatically adjust its fram-
ing. The word boundary is aligned at the appropriate bit po-
sition and the parallel output clock is aligned with the appro-
priate cycle of the serial clock. When FE is held low and a
TRS, out of phase with the current PCLK, is received, output
NSP will go high. However, the phase of PCLK will not be ad-
justed. NSP will remain high until a TRS, in-phase with the
current PCLK, is received.
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