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PDF S6E1A12B0A Data sheet ( Hoja de datos )

Número de pieza S6E1A12B0A
Descripción Microcontroller
Fabricantes Cypress Semiconductor 
Logotipo Cypress Semiconductor Logotipo



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No Preview Available ! S6E1A12B0A Hoja de datos, Descripción, Manual

S6E1A11B0A/C0A
S6E1A12B0A/C0A
32-Bit ARM® Cortex®
FM0+ based Microcontroller
The S6E1A1 Series is a series of highly integrated 32-bit microcontrollers designed for embedded controllers aiming at low power
consumption and low cost.
This series has the ARM Cortex-M0+ Processor with on-chip Flash memory and SRAM, and consists of peripheral functions such
as various timers, ADCs and communication interfaces (UART, CSIO, I2C, LIN).
The products which are described in this data sheet are placed into TYPE1-M0+ product categories in "FM0+ Family PERIPHERAL
MANUAL".
Features
32-bit ARM Cortex-M0+ Core
Processor version: r0p1
Maximum operating frequency: 40 MHz
Nested Vectored Interrupt Controller (NVIC): 1 NMI
(non-maskable interrupt) and 32 peripheral interrupt with 4
selectable interrupt priority levels
24-bit System timer (Sys Tick): System timer for OS task
management
Bit Band operation
Compatible with Cortex-M3 bit band operation
On-Chip Memories
Flash memory
Up to 88 Kbyte
Read cycle:0 wait-cycle
Security function for code protection
SRAM
The on-chip SRAM of this series has one independent SRAM.
SRAM: 6 Kbyte
Multi-function Serial Interface (Max 3channels)
128 bytes with FIFO in all channels (The number of FIFO
steps varies depending on the settings of the communication
mode or bit length.)
The operation mode of each channel can be selected from
one of the following.
UART
CSIO
LIN
I2C
UART
Full duplex double buffer
Parity can be enabled or disabled.
Built-in dedicated baud rate generator
External clock available as a serial clock
Various error detection functions (parity errors, framing errors,
and overrun errors)
CSIO
Full duplex double buffer
Built-in dedicated baud rate generator
Overrun error detection function
Serial chip select function (ch.1 and ch.3 only)
Data length: 5 to 16 bits
LIN
LIN protocol Rev.2.1 supported
Full duplex double buffer
Master/Slave mode supported
LIN break field generation function (The length is variable
between 13 bits and 16 bits.)
LIN break delimiter generation function (The length is
variable between 1 bit and 4 bits.)
Various error detection functions available (parity errors,
framing errors, and overrun errors)
I2C
Standard-mode (Max: 100 kbps) supported / Fast-mode
(Max 400kbps) supported.
DMA Controller (2 channels)
The DMA Controller has its own bus independent of the CPU,
and CPU and DMA Controller can process simultaneously.
2 independently configurable and operable channels
It can start a transfer with a software request or a request
from a built-in peripheral.
Transfer address area: 32 bits (4 Gbyte)
Transfer mode: block transfer/burst transfer/demand transfer
Transfer data type: byte/halfword/word
Transfer block count: 1 to 16
Number of transfers: 1 to 65536
Cypress Semiconductor Corporation
Document Number: 002-05091 Rev.*A
• 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Revised February 10, 2016

1 page




S6E1A12B0A pdf
S6E1A11B0A/C0A
S6E1A12B0A/C0A
1. Product Lineup
Memory Size
Product name
On-chip Flash memory
On-chip SRAM
56 Kbyte
6 Kbyte
S6E1A11B0A
S6E1A11C0A
Function
Product name
Pin count
CPU
Frequency
Power supply voltage range
DMAC
Multi-function Serial Interface
(UART/CSIO/I2C)
Base Timer
(PWC/Reload timer/PWM/PPG)
A/D start compare
Multi-functio
n
Timer
QPRC
Input capture
Free-run timer
Output compare
Waveform
generator
PPG
Dual Timer
Real-time Clock
Watch Counter
Watchdog timer
External Interrupt
I/O port
12-bit A/D converter
CSV (Clock Supervisor)
LVD (Low-voltage Detection)
Built-in CR
High-speed
Low-speed
Debug Function
Unique ID
S6E1A11B0A
S6E1A12B0A
32
Cortex-M0+
40 MHz
2.7 V to 5.5 V
2 ch.
3 ch. (Max)
ch.0/ch.1/ch.3: FIFO
4 ch. (Max)
6 ch.
4 ch.
3 ch.
6 ch.
3 ch.
3 ch.
1 unit
1 ch.
1 unit
1 unit
1 unit
1 ch. (SW) + 1 ch. (HW)
8 pins (Max) + NMI × 1
23 pins (Max)
5 ch. (1 unit)
Yes
2 ch.
4 MHz
100 kHz
SW-DP
Yes
88 Kbyte
6 Kbyte
S6E1A12B0A
S6E1A12C0A
48/52
S6E1A11C0A
S6E1A12C0A
37 pins (Max)
8 ch. (1 unit)
Note:
All signals of the peripheral function in each product cannot be allocated by limiting the pins of package. It is necessary to use
the port relocate function of the I/O port according to your function use.
See "14. ELECTRICAL CHARACTERISTICS 14.4 AC Characteristics 14.4.3 Built-in CR Oscillation Characteristics" for
accuracy of built-in CR.
Document Number: 002-05091 Rev.*A
Page 5 of 95

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S6E1A12B0A arduino
FPT-52P-M02
(TOP VIEW)
S6E1A11B0A/C0A
S6E1A12B0A/C0A
VCC 1
P50/INT00_0/AIN0_2/SIN3_1/IC01_0 2
P51/INT01_0/BIN0_2/SOT3_1 3
P52/INT02_0/ZIN0_2/SCK3_1 4
NC 5
P39/DTTI0X_0/ADTG_2 6
P3A/RTO00_0/TIOA0_1/AIN0_3/SUBOUT_2/RTCCO_2/INT03_0/SCK0_2 7
P3B/RTO01_0/TIOA1_1/BIN0_3/SOT0_2/INT04_0/SCS31_2 8
P3C/RTO02_0/TIOA2_1/ZIN0_3/SIN0_2/INT05_0/SCS30_2 9
P3D/RTO03_0/TIOA3_1/INT06_0/AIN0_0/SCK3_2 10
P3E/RTO04_0/TIOA0_0/BIN0_0/SOT3_2/INT15_0 11
P3F/RTO05_0/TIOA1_0/ZIN0_0/SIN3_2 12
VSS 13
LQFP - 52
39 P21/SIN0_0/INT06_1/TIOB1_1/IC01_1/BIN0_1/FRCK0_0
38 P22/AN07/SOT0_0/TIOB2_0/IC03_1/ZIN0_1/INT05_1
37 P23/AN06/SCK0_0/TIOA2_0/IC02_1/AIN0_1/INT04_1
36 NC
35 AVSS
34 AVRH
33 AVCC
32 P15/AN05/SOT0_1/SCS11_1/IC03_2/INT15_2
31 P14/AN04/SIN0_1/SCS10_1/INT03_1/IC02_2
30 P13/AN03/SCK1_1/SUBOUT_1/IC01_2/RTCCO_1/INT00_1
29 P12/AN02/SOT1_1/IC00_2/INT01_1
28 P11/AN01/SIN1_1/INT02_1/FRCK0_2/IC02_0
27 P10/AN00
Note:
The number after the underscore ("_") in a pin name such as XXX_1 and XXX_2 indicates the relocated port number. The
channel on such pin has multiple functions, each of which has its own pin name. Use the Extended Port Function Register
(EPFR) to select the pin to be used.
Document Number: 002-05091 Rev.*A
Page 11 of 95

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