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PDF FM25V10 Data sheet ( Hoja de datos )
| Número de pieza | FM25V10 | |
| Descripción | 1Mb Serial 3V F-RAM Memory | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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FM25V10
1-Mbit (128K × 8) Serial (SPI) F-RAM
1-Mbit (128K × 8) Serial (SPI) F-RAM
Features
■ 1-Mbit ferroelectric random access memory (F-RAM) logically
organized as 128K × 8
❐ High-endurance 100 trillion (1014) read/writes
❐ 151-year data retention (See the Data Retention and
Endurance table)
❐ NoDelay™ writes
❐ Advanced high-reliability ferroelectric process
■ Very fast serial peripheral interface (SPI)
❐ Up to 40-MHz frequency
❐ Direct hardware replacement for serial flash and EEPROM
❐ Supports SPI mode 0 (0, 0) and mode 3 (1, 1)
■ Sophisticated write protection scheme
❐ Hardware protection using the Write Protect (WP) pin
❐ Software protection using Write Disable instruction
❐ Software block protection for 1/4, 1/2, or entire array
■ Device ID and Serial Number
❐ Manufacturer ID and Product ID
❐ Unique Serial Number (FM25VN10)
■ Low power consumption
❐ 300 A active current at 1 MHz
❐ 90 A (typ) standby current
❐ 5 A sleep mode current
■ Low-voltage operation: VDD = 2.0 V to 3.6 V
■ Industrial temperature: –40 C to +85 C
■ Packages
❐ 8-pin small outline integrated circuit (SOIC) package
❐ 8-pin dual flat no-leads (DFN) package
■ Restriction of hazardous substances (RoHS) compliant
Functional Description
The FM25V10 is a 1-Mbit nonvolatile memory employing an
advanced ferroelectric process. A ferroelectric random access
memory or F-RAM is nonvolatile and performs reads and writes
similar to a RAM. It provides reliable data retention for 151 years
while eliminating the complexities, overhead, and system-level
reliability problems caused by serial flash, EEPROM, and other
nonvolatile memories.
Unlike serial flash and EEPROM, the FM25V10 performs write
operations at bus speed. No write delays are incurred. Data is
written to the memory array immediately after each byte is
successfully transferred to the device. The next bus cycle can
commence without the need for data polling. In addition, the
product offers substantial write endurance compared with other
nonvolatile memories. The FM25V10 is capable of supporting
1014 read/write cycles, or 100 million times more write cycles
than EEPROM.
These capabilities make the FM25V10 ideal for nonvolatile
memory applications, requiring frequent or rapid writes.
Examples range from data collection, where the number of write
cycles may be critical, to demanding industrial controls where the
long write time of serial flash or EEPROM can cause data loss.
The FM25V10 provides substantial benefits to users of serial
EEPROM or flash as a hardware drop-in replacement. The
FM25V10 uses the high-speed SPI bus, which enhances the
high-speed write capability of F-RAM technology. The
FM25VN10 is offered with a unique serial number that is
read-only and can be used to identify a board or system. Both
the devices incorporates a read-only Device ID that allows the
host to determine the manufacturer, product density, and product
revision. The device specifications are guaranteed over an
industrial temperature range of –40 C to +85 C.
For a complete list of related documentation, click here.
Logic Block Diagram
WP
CS
HOLD
SCK
SI
Instruction Decoder
Clock Generator
Control Logic
Write Protect
Instruction Register
Address Register
Counter
17
128 K x 8
F-RAM Array
8
Data I/O Register
3
Nonvolatile Status
Register
SO
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-84499 Rev. *H
• San Jose, CA 95134-1709 • 408-943-2600
Revised August 30, 2016
1 page  
FM25V10
For a microcontroller that has no dedicated SPI bus, a
general-purpose port may be used. To reduce hardware
resources on the controller, it is possible to connect the two data
pins (SI, SO) together and tie off (HIGH) the HOLD and WP pins.
Figure 4 shows such a configuration, which uses only three pins.
Most Significant Bit (MSB)
The SPI protocol requires that the first bit to be transmitted is the
Most Significant Bit (MSB). This is valid for both address and
data transmission.
The 1-Mbit serial F-RAM requires a 3-byte address for any read
or write operation. Because the address is only 17 bits, the first
seven bits, which are fed in are ignored by the device. Although
these seven bits are ‘don’t care’, Cypress recommends that
these bits be set to 0s to enable seamless transition to higher
memory densities.
Serial Opcode
After the slave device is selected with CS going LOW, the first
byte received is treated as the opcode for the intended operation.
FM25V10 uses the standard opcodes for memory accesses.
Invalid Opcode
If an invalid opcode is received, the opcode is ignored and the
device ignores any additional serial data on the SI pin until the
next falling edge of CS, and the SO pin remains tristated.
Status Register
FM25V10 has an 8-bit Status Register. The bits in the Status
Register are used to configure the device. These bits are
described in Table 3 on page 7.
Figure 3. System Configuration with SPI Port
SCK
MOSI
MISO
SPI
Microcontroller
CS1
HOLD1
WP1
CS2
HOLD2
WP2
SCK SI SO
FM25V10
CS HOLD WP
SCK SI SO
FM25V10
CS HOLD WP
Figure 4. System Configuration without SPI Port
P1.0
P1.1
Microcontroller
SCK SI SO
FM25V10
CS HOLD WP
P1.2
SPI Modes
FM25V10 may be driven by a microcontroller with its SPI
peripheral running in either of the following two modes:
■ SPI Mode 0 (CPOL = 0, CPHA = 0)
■ SPI Mode 3 (CPOL = 1, CPHA = 1)
For both these modes, the input data is latched in on the rising
edge of SCK starting from the first rising edge after CS goes
active. If the clock starts from a HIGH state (in mode 3), the first
rising edge after the clock toggles is considered. The output data
is available on the falling edge of SCK.
Document Number: 001-84499 Rev. *H
Page 5 of 25
5 Page 
FM25V10
Sleep Mode
A low-power sleep mode is implemented on the FM25V10
device. The device will enter the low-power state when the
SLEEP opcode B9h is clocked in and a rising edge of CS is
applied. When in sleep mode, the SCK and SI pins are ignored
and SO will be HI-Z, but the device continues to monitor the CS
pin. On the next falling edge of CS, the device will return to
normal operation within tREC time. The SO pin remains in a HI-Z
state during the wakeup period. The device does not necessarily
respond to an opcode within the wakeup period. To start the
wakeup procedure, the controller may send a “dummy” read, for
example, and wait the remaining tREC time.
CS
SCK
Figure 15. Sleep Mode Operation
Enters Sleep Mode
tREC Recovers from Sleep Mode
0123 456 7
t SU
SI 1 0 1 1 1 0 0 1
SO HI-Z
VALID IN
Device ID
The FM25V10 device can be interrogated for its manufacturer,
product identification, and die revision. The RDID opcode 9Fh
allows the user to read the manufacturer ID and product ID, both
of which are read-only bytes. The JEDEC-assigned
manufacturer ID places the Cypress (Ramtron) identifier in
bank 7; therefore, there are six bytes of the continuation code
7Fh followed by the single byte C2h. There are two bytes of
product ID, which includes a family code, a density code, a sub
code, and the product revision code.
Table 6. Device ID
Device ID Description
Device ID
(9 bytes)
71–16
(56 bits)
Manufacturer ID
15–13
(3 bits)
Family
12–8
(5 bits)
Density
7–6
(2 bits)
Product ID
Sub
5–3
(3 bits)
Rev
2–0
(3 bits)
Rsvd
7F7F7F7F7F7FC22400h
0111111101111111011111110111
1111011111110111111111000010
001
00100
00
000 000
Figure 16. Read Device ID
CS
SCK
SI
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71
Opcode
1 001 11 11
HI-Z
SO
D7 D6 D5 D4 D3 D2 D1 D0
MSB
D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
9-Byte Device ID
LSB
Document Number: 001-84499 Rev. *H
Page 11 of 25
11 Page | ||
| Páginas | Total 25 Páginas | |
| PDF Descargar | [ Datasheet FM25V10.PDF ] | |
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