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PDF BD8163EFV Data sheet ( Hoja de datos )
| Número de pieza | BD8163EFV | |
| Descripción | 5V Input Multi-channel System Power Supply ICs | |
| Fabricantes | ROHM Semiconductor | |
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Power Supply ICs for TFT-LCD Panels
5V Input Multi-channel
System Power Supply ICs
BD8163EFV
No.10035EAT13
●Description
The BD8163EFV is a system power supply IC for TFT panels. A 1-chip IC providing a total of four voltages required for TFT
panels, i.e., logic voltage, sauce voltage, gate high-level, and gate low-level voltage, thus constructing a TFT panel power
supply with minimal components required.
●Features
1) Operates in an operating voltage range as low as 2.1 V to 6. 0 V.
2) Incorporates a step-up DC/DC converter.
3) Incorporates a 2.5 V regulator.
4) Incorporates positive and negative-side charge pumps.
5) Switching frequency of 1100 kHz
6) DC/DC converter feedback voltage of 1.24 V ± 1%
7) Incorporates a gate shading function
8) Under-voltage lockout protection circuit
9) Thermal shutdown circuit
10) Overcurrent protection circuit
11) HTSSOP-B24 package
●Applications
Liquid crystal TV, PC monitor, and TFT-LCD panel
●Absolute maximum ratings (Ta = 25℃)
Parameter
Symbol
Ratings
Unit
Power supply voltage
VCC
7
Vo1 voltage
Vo1 19
Vo2 voltage
Vo2 32
SW voltage
Vsw 19
Maximum junction temperature
Tjmax
150
Power dissipation
Pd 1100*
Operating temperature range
Topr -40 to 125
Storage temperature range
Tstg -55 to 150
* Reduced by 4.7 mW/℃ over 25℃, when mounted on a glass epoxy board. (70 mm 70 mm 1.6 mm).
V
V
V
V
℃
mW
℃
℃
●Recommended Operating Ranges
Parameter
Power supply voltage
Vo1 voltage
Vo2 voltage
SW Current
Vo2 Current
Symbol
VCC
Vo1
Vsw
Isw
Vo2
Ratings
Min. Max.
2.1 6
8 18
— 18
— 1.8
— 30
Unit
V
V
V
A
V
www.rohm.com
© 2010 ROHM Co., Ltd. All rights reserved.
1/21
2010.12 - Rev.A
1 page  
BD8163EFV
●Reference Data (Unless otherwise specified, Ta = 25℃)
1 10
0.8 125℃
0.6
25℃
0.4
0.2
-40℃
0
0 1.5 3 4.5 6
SUPPLY VOLTAGE : VCC [V]
Fig. 1 Total Supply Current 1
8
6
25℃
4
125℃
2
-40℃
0
0 1.5 3 4.5 6
SUPPLY VOLTAGE : VDD[V]
Fig. 2 Total Supply Current 2
1.6
1.2
0.8
0.4
0
0 1.5 3 4.5 6
SUPPLY VOLTAGE : VCC[V]
Fig. 4 Internal
Reference Line Regulation
12
10
8
6
4
2
0
0 1.5 3 4.5 6
SUPPLY VOLTAGE : VDD[V]
Fig. 7 DLS Source Current
200
160
120
80
40
0
0 0.2 0.4 0.6 0.8 1
SW CURRENT : ISW [A]
Fig. 10 SW On Resistance
1.6
1.2
0.8
0.4
0
0 5 10 15 20 25 30
REF CURRENT : IREF[mA]
Fig. 5 Internal
Reference Load Regulation
2
1.5
1
0.5
0
-450 -25 0 25 50 75 100 125
AMBIENT TEMPERATURE : Ta[℃]
Fig. 8 Switching Frequency
Temperature
200
160
120
N channel
80
P channel
40
0
0 20 40 60 80 100
INPUT CURRENT : Icp[mA]
Fig. 11 Charge Pump
On Voltage
Technical Note
1.26
1.25
1.24
1.23
1.22
-50 -25 0 25 50 75 100 125
AMBIENT TEMPERATURE : Ta[℃]
Fig. 3 Internal Reference
Temperature
12
10
8
6
4
2
0
0 1.5 3 4.5
SUPPLY VOLTAGE : VDD[V]
6
Fig. 6 SS Source Current
5
4
3
2
1
0
0 2 4 6 8 10
BASE CURRENT : IBASE[mA]
Fig. 9 REG Current Capacity
1
0.8
0.6
N channel
0.4
0.2
P channel
0 0 20 40 60 80 100
GS CURRENT : Igs[mA]
Fig. 12 Gate Shading
On Voltage
www.rohm.com
© 2010 ROHM Co., Ltd. All rights reserved.
5/21
2010.12 - Rev.A
5 Page 
BD8163EFV
Technical Note
(4) Setting RC, CC of the Phase Compensation Circuit
In the current mode control, since the coil current is controlled, a pole (phase lag) made by the CR filter composed of the
output capacitor and load resistor will be created in the low frequency range, and a zero (phase lead) by the output
capacitor and ESR of capacitor will be created in the high frequency range. In this case, to cancel the pole of the power
amplifier, it is easy to compensate by adding the zero point with CC and RC to the output from the error amp as shown in
the illustration.
Open loop gain characteristics
A fp(Min)
fp(Max)
Gain 0
Fp =
fz(ESR) =
1
2 RO CO
1
2 ESR CO
[Hz]
[Hz]
[dB]
lOUTMin
lOUTMax
fz(ESR)
0
Phase
Pole at the power amplification stage
When the output current reduces, the load resistance
Ro increases and the pole frequency lowers.
[deg] -90
fp(Min) =
1
2 ROMax CO
[Hz] at light load
Error amp phase
compensation characteristics
Gain
[dB]
A
0
Phase 0
[deg] -90
fz(Max) =
1
2 ROMin CO
[Hz] at heavy load
Zero at the power amplification stage
When the output capacitor is set larger, the pole
frequency lowers but the zero frequency will not
change. (This is because the capacitor ESR becomes
1/2 when the capacitor becomes 2 times.)
1
fp(Amp.) = 2 Rc Cc
[Hz]
Fig. 29 Gain vs Phase
L
Vo
VCC Cin
Rc
Cc
Vcc,PVcc
COMP
SW
GND,PGND
ESR
Co
Ro
Fig. 30 Application Circuit Diagram
It is possible to realize the stable feedback loop by canceling the pole fp(Min.), which is created by the output capacitor
and load resistor, with CR zero compensation of the error amp as shown below.
fz(Amp.) = fp(Min.)
1
2 Rc Cc
=
1 [Hz]
2 Romax Co
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© 2010 ROHM Co., Ltd. All rights reserved.
11/21
2010.12 - Rev.A
11 Page | ||
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