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PDF GS8342Q18BD-250 Data sheet ( Hoja de datos )

Número de pieza GS8342Q18BD-250
Descripción 36Mb SigmaQuad-II Burst of 2 SRAM
Fabricantes GSI Technology 
Logotipo GSI Technology Logotipo



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No Preview Available ! GS8342Q18BD-250 Hoja de datos, Descripción, Manual

165-Bump BGA
Commercial Temp
Industrial Temp
GS8342Q08/09/18/36BD-357/333/300/250
36Mb SigmaQuad-IITM
Burst of 2 SRAM
357 MHz–250 MHz
1.8 V VDD
1.8 V and 1.5 V I/O
Features
• Simultaneous Read and Write SigmaQuad™ Interface
• JEDEC-standard pinout and package
• Dual Double Data Rate interface
• Byte Write controls sampled at data-in time
• Burst of 2 Read and Write
• 1.8 V +100/–100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• Pipelined read operation
• Fully coherent read and write pipelines
• ZQ pin for programmable output drive strength
• IEEE 1149.1 JTAG-compliant Boundary Scan
• Pin-compatible with present 144 Mb devices
• 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package
• RoHS-compliant 165-bump BGA package available
SigmaQuadFamily Overview
The GS8342Q08/09/18/36BD are built in compliance with the
SigmaQuad-II SRAM pinout standard for Separate I/O
synchronous SRAMs. They are 37,748,736-bit (36Mb)
SRAMs. The GS8342Q08/09/18/36BD SigmaQuad SRAMs
are just one element in a family of low power, low voltage
HSTL I/O SRAMs designed to operate at the speeds needed to
implement economical high performance networking systems.
Clocking and Addressing Schemes
The GS8342Q08/09/18/36BD SigmaQuad-II SRAMs are
synchronous devices. They employ two input register clock
inputs, K and K. K and K are independent single-ended clock
inputs, not differential inputs to a single differential clock input
buffer. The device also allows the user to manipulate the
output register clock inputs quasi independently with the C and
C clock inputs. C and C are also independent single-ended
clock inputs, not differential inputs. If the C clocks are tied
high, the K clocks are routed internally to fire the output
registers instead.
Each internal read and write operation in a SigmaQuad-II B2
RAM is two times wider than the device I/O bus. An input data
bus de-multiplexer is used to accumulate incoming data before
it is simultaneously written to the memory array. An output
data multiplexer is used to capture the data produced from a
single memory array read and then route it to the appropriate
output drivers as needed. Therefore the address field of a
SigmaQuad-II B2 RAM is always one address pin less than the
advertised index depth (e.g., the 4M x 8 has an 2M addressable
index).
tKHKH
tKHQV
Parameter Synopsis
-357
2.8 ns
0.45 ns
-333
3.0 ns
0.45 ns
-300
3.3 ns
0.45 ns
-250
4.0 ns
0.45 ns
Rev: 1.02b 4/2014
1/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology

1 page




GS8342Q18BD-250 pdf
GS8342Q08/09/18/36BD-357/333/300/250
4M x 9 SigmaQuad-II SRAM — Top View
123456789
A
CQ
NC/SA
(72Mb)
SA
W
NC
K
NC/SA
(144Mb)
R
SA
B
NC
NC
NC
SA
NC/SA
(288Mb)
K
BW0 SA
NC
C NC NC NC VSS SA SA SA VSS NC
D NC D5 NC VSS VSS VSS VSS VSS NC
E
NC
NC
Q5
VDDQ
VSS
VSS
VSS VDDQ NC
F
NC
NC
NC
VDDQ
VDD
VSS
VDD VDDQ NC
G
NC D6
Q6
VDDQ
VDD
VSS
VDD VDDQ NC
H
Doff
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
J
NC
NC
NC
VDDQ
VDD
VSS
VDD VDDQ NC
K
NC
NC
NC
VDDQ
VDD
VSS
VDD VDDQ NC
L
NC
Q7
D7
VDDQ
VSS
VSS
VSS VDDQ NC
M NC NC NC VSS VSS VSS VSS VSS NC
N NC D8 NC VSS SA SA SA VSS NC
P NC NC Q8 SA SA C SA SA NC
R
TDO TCK
SA
SA
SA
C
SA SA SA
11 x 15 Bump BGA—13 x 15 mm Body—1 mm Bump Pitch
Notes:
1. BW0 controls writes to DQ:D8.
2. A2, A7, and B5 are the expansion addresses.
10
SA
NC
NC
NC
D3
NC
NC
VREF
Q2
NC
NC
NC
NC
D0
TMS
11
CQ
Q4
D4
NC
Q3
NC
NC
ZQ
D2
NC
Q1
D1
NC
Q0
TDI
Rev: 1.02b 4/2014
5/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology

5 Page





GS8342Q18BD-250 arduino
GS8342Q08/09/18/36BD-357/333/300/250
Rev: 1.02b 4/2014
11/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology

11 Page







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