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PDF 555 Data sheet ( Hoja de datos )

Número de pieza 555
Descripción Single Timer
Fabricantes Fairchild Semiconductor 
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555 datasheet pdf


1. LinCMOS Timer ( TLC555 )






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No Preview Available ! 555 Hoja de datos, Descripción, Manual

January 2013
LM555
Single Timer
Features
• High-Current Drive Capability: 200 mA
• Adjustable Duty Cycle
• Temperature Stability of 0.005%/°C
• Timing From μs to Hours
• Turn off Time Less Than 2 μs
Applications
• Precision Timing
• Pulse Generation
• Delay Generation
• Sequential Timing
Description
The LM555 is a highly stable controller capable of pro-
ducing accurate timing pulses. With a monostable opera-
tion, the delay is controlled by one external resistor and
one capacitor. With astable operation, the frequency and
duty cycle are accurately controlled by two external
resistors and one capacitor.
8-DIP
1
8-SOIC
1
Ordering Information
Part Number
LM555CN
LM555CM
LM555CMX
Operating Temperature Range
0 ~ +70°C
Top Mark
LM555CN
LM555CM
LM555CM
Package
DIP 8L
SOIC 8L
SOIC 8L
Packing Method
Rail
Rail
Tape & Reel
© 2002 Fairchild Semiconductor Corporation
LM555 Rev. 1.1.0
1
www.fairchildsemi.com

1 page




555 pdf
1. Monostable Operation
Figure 2 illustrates a monostable circuit. In this mode, the timer generates a fixed pulse whenever the trigger voltage
falls below VCC/3. When the trigger pulse voltage applied to the #2 pin falls below VCC/3 while the timer output is low,
the timer's internal flip-flop turns the discharging transistor off and causes the timer output to become high by charging
the external capacitor C1 and setting the flip-flop output at the same time.
The voltage across the external capacitor C1, VC1 increases exponentially with the time constant t = RA*C and
reaches 2 VCC/3 at tD = 1.1 RA*C. Hence, capacitor C1 is charged through resistor RA. The greater the time constant
RAC, the longer it takes for the VC1 to reach 2 VCC/3. In other words, the time constant RAC controls the output pulse
width.
When the applied voltage to the capacitor C1 reaches 2 VCC/3, the comparator on the trigger terminal resets the flip-
flop, turning the discharging transistor on. At this time, C1 begins to discharge and the timer output converts to low.
In this way, the timer operating in the monostable repeats the above process. Figure 3 shows the time constant rela-
tionship based on RA and C. Figure 4 shows the general waveforms during the monostable operation.
It must be noted that, for a normal operation, the trigger pulse voltage needs to maintain a minimum of VCC/3 before
the timer output turns low. That is, although the output remains unaffected even if a different trigger pulse is applied
while the output is high, it may be affected and the waveform does not operate properly if the trigger pulse voltage at
the end of the output pulse remains at below VCC/3. Figure 5 shows such a timer output abnormality.
Figure 5. Waveforms of Monostable Operation
(abnormal)
2. Astable Operation
4
RESET
2 TRIG
8
Vcc
DISCH 7
THRES 6
+Vcc
RA
RB
100
10
1
0.1
(RA+2RB)
3 OUT
GND
CONT 5
C1
RL 1
C2
0.01
1E-3
100m
1
10 100 1k
Frequency(Hz)
10k 100k
Figure 6. A Stable Circuit
Figure 7. Capacitance and Resistance vs. Frequency
© 2002 Fairchild Semiconductor Corporation
LM555 Rev. 1.1.0
5
www.fairchildsemi.com

5 Page





555 arduino
Physical Dimensions
8-DIP
A
(.092) [Ø2.337]
PIN #1
[ ].400 10.15
.373 9.46
.036 [0.9 TYP]
.250±.005 [6.35±0.13]
(.032) [R0.813]
PIN #1
TOP VIEW
OPTION 1
7° TYP
B
[ ].070 1.78
.045 1.14
.310±.010 [7.87±0.25]
.130±.005 [3.3±0.13]
.210 MAX
[5.33]
7° TYP
TOP VIEW
OPTION 2
C
[ ].021 0.53
.015 0.37
.001[.025]
C
.015 MIN
[0.38]
[ ].140 3.55
.125 3.17
.100
[2.54]
NOTES:
A. CONFORMS TO JEDEC REGISTRATION MS-001,
VARIATIONS BA
B. CONTROLING DIMENSIONS ARE IN INCHES
REFERENCE DIMENSIONS ARE IN MILLIMETERS
C. DOES NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED
.010 INCHES OR 0.25MM.
D. DOES NOT INCLUDE DAMBAR PROTRUSIONS.
DAMBAR PROTRUSIONS SHALL NOT EXCEED
.010 INCHES OR 0.25MM.
E. DIMENSIONING AND TOLERANCING
PER ASME Y14.5M-1994.
.300
[7.62]
.430 MAX
[10.92]
.060 MAX
[1.52]
[ ].010+-..000005 0.254+-00..010207
N08EREVG
Figure 16. 8-Lead, DIP, JEDEC MS-001, 300" WIDE
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
For current tape and reel specifications, visit Fairchild Semiconductor’s online packaging area:
http://www.fairchildsemi.com/products/discrete/pdf/8dip_tr.pdf.
© 2002 Fairchild Semiconductor Corporation
LM555 Rev. 1.1.0
11
www.fairchildsemi.com

11 Page







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