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PDF SiI9573 Data sheet ( Hoja de datos )
| Número de pieza | SiI9573 | |
| Descripción | Port Processor | |
| Fabricantes | Lattice | |
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SiI9573 and SiI9575 Port Processor
Data Sheet
SiI-DS-1089-F
March 2016
1 page  
SiI9573 and SiI9575 Port Processor
Data Sheet
Figure 6.33. 8-bit Color Depth YC Mux 4:2:2 Embedded Sync Dual Edge Timing (DRA = 1, YCSWAP = 1) .....................65
Figure 6.34. 10-bit Color Depth YC Mux 4:2:2 Embedded Sync Dual Edge Timing (DRA = 0, YCSWAP = 0)...................66
Figure 6.35. 10-bit Color Depth YC Mux 4:2:2 Embedded Sync Dual Edge Timing (DRA = 1, YCSWAP = 0)...................67
Figure 6.36. 12-bit Color Depth YC Mux 4:2:2 Embedded Sync Dual Edge Timing (DRA = 0, YCSWAP = 0)...................68
Figure 6.37. 12-bit Color Depth YC Mux 4:2:2 Embedded Sync Dual Edge Timing (DRA = 1, YCSWAP = 0)...................68
Figure 7.1. Decoupling and Bypass Schematic...............................................................................................................69
Figure 7.2. Decoupling and Bypass Capacitor Placement ..............................................................................................69
Figure 8.1. Package Diagram..........................................................................................................................................71
Figure 8.2. Marking Diagram .........................................................................................................................................72
© 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1089-F
5
5 Page 
SiI9573 and SiI9575 Port Processor
Data Sheet
2.1.7. Configuration, Status, and Interrupt Control Block
The Configuration, Status, and Interrupt Control Registers Block incorporate the registers required for configuring and
managing the features of the SiI957n port processor. These registers are grouped by functions such as RPI, TPI, CPI,
MHL, and miscellaneous and are used to perform audio, video, and auxiliary format processing, HDMI 1.4a InfoFrame
Packet format, and power-down control. The registers are accessible from the local I2C port. This block also handles
interrupt operation.
2.1.8. Mobile HD Control Block
The Mobile HD Control Block handles MHL DDC control. This block handles CBUS conversion to DDC signals for
accessing the EDID and HDCP interface blocks.
2.1.9. CEC Interface Controller
Two independent Consumer Electronics Control (CEC) interface controllers are available in the SiI957n port processor.
This gives the system designer the option to design a system that supports both primary CEC line and a secondary CEC
line that are not physically connected to each other. For example, using an AVR featuring two DTV connections from the
SiI957n device, the primary CEC line (CEC_A0 pin) can be connected to the CEC signal of all HDMI input ports of the AVR
while the secondary CEC line (CEC_A1 pin) connects to the CEC signal of the second DTV.
Each CEC interface controller provides a CEC-compliant signal and has a high-level register interface accessible through
the I2C interface. Programming is done through the Lattice Semiconductor CEC Programming Interface (CPI). This
controller makes CEC control easy and straightforward by removing the burden of requiring that the host processor
perform these low-level transactions on the CEC bus. As a result, CEC pass-through mode is neither required nor
supported.
The CEC controllers (CEC_A0 and CEC_A1) are identical except for the device address used to access them.
2.1.10. Power Block
The Power Block features an analog power multiplexer with inputs from the +5 V power from the R[0–5]PWR5V and the
SBVCC5V sources. The output of the analog power multiplexer supplies power to the Always-On Section.
2.2. Power-down Section
The Power-down Section contains the HDMI high-speed data paths, including the analog TMDS input and output blocks
and the digital logic for HDMI data and HDCP processing.
2.2.1. TMDS Receiver Blocks
The TMDS Receiver Blocks, defined as Port 0, Port 1, Port 2, Port 3, Port 4, and Port 5, are terminated separately,
equalized under the control of the receiver digital block, and controlled by the local I2C bus. Input data is over-sampled
by five to enable the downstream DPLL block to capture the most stable signal at any given time.
2.2.2. 6:1 Input Multiplexer Blocks A and B and 4:1 Input Multiplexer Blocks C and D
6:1 Input Multiplexer Block A selects one of the six TMDS inputs and sends it to the main pipe. 6:1 Input Multiplexer
Block B selects one of the six TMDS inputs and sends it to the subpipe. 4:1 Input Multiplexer Block C selects among
main pipe, subpipe, parallel video, and video pattern generator sources and sends it to HDMI output Tx0. 4:1 Input
Multiplexer Block D selects among main pipe, subpipe, parallel video, and video pattern generator sources and sends it
to HDMI output Tx1. The specific function of the multiplexers is determined by whether InstaPort, InstaPrevue, or
matrix switch mode is enabled.
In InstaPort or InstaPrevue modes, Multiplexer Block A selects the active input and sends it to the main pipe for
processing. The subpipe functions as a roving pipe whereby Multiplexer Block B sequentially selects one of the five
inactive inputs and sends it to the InstaPort or InstaPrevue blocks for processing. Multiplexer Blocks C and D can each
independently select among main pipe, parallel video, and video pattern generator sources to send to HDMI output Tx0
and Tx1 respectively.
© 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1089-F
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SiI9573.PDF ] | |
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