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PDF RT9264 Data sheet ( Hoja de datos )

Número de pieza RT9264
Descripción Step-up DC/DC Converter
Fabricantes RICHTEK 
Logotipo RICHTEK Logotipo



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Preliminary
RT9264
High Frequency, High Efficiency, Step-up DC/DC Converter
General Description
The RT9264 is a compact, high efficient, step-up
DC/DC converter with current mode PWM control
loop, providing stable and high efficient operations
without external compensation.
The RT9264 suitable for 1 to 4 battery cells as well
as USB power applications providing up to 400mA
output current. The high switching rate minimized
the size of external components.
A 300mA LDO is included in RT9264 to provide a
secondary low noise output as well as an output
current stop in the shutdown mode. RT9264 is
provided in SOP-8 packages.
Ordering Information
RT9264… …
Package type
S : SOP-8
Operating temperature range
C: Commercial standard
Typical Application Circuit
Features
z 400mA High Supply Capability
z 90% Efficiency
z Switching Rate higher Than 1.4MHz
z Providing Flexibility for Using Internal and
External Power Switches
z Built-in 300mA LDO, also for the Zero-Output-
Current Shutdown Mode
z Boost DC-DC Integrating LDO for Up-Down
Regulation
z 8-Pin SOP Package
Applications
z Portable Instrument
z ADSL Modem
z USB Devices
Pin Configurations
Part Number
RT9264CS
(Plastic SOP-8)
Pin Configurations
TOP VIEW
GND 1
EXT 2
8 CE
7 LX
LFB 3
LDOO 4
6 VDD
5 FB
VIN
2.5V
VOU T2
C3
10µF
VDD
CE RT9264
R4 L DO O
42K L F B
GND
R3
22K
EXT
LX
FB
L1
R1 2.2µH
36K D1
1N5819
R2 C2
22K 1µF
47µF
3.3V
VOU T1
C1
47µF
Fig. 1 RT9264 Typical Application for Portable Instruments
DS9264-00 December 2001
www.richtek-ic.com.tw
1

1 page




RT9264 pdf
Preliminary
RT9264
Application Note
Output Voltage Setting
Referring to application circuits Fig.1 to Fig.3, the
output voltage of the switching regulator (VOUT1) can
be set with Eq.1.
The LDO output voltage can be set with Eq.2.
VOUT1 = (1+ RR21) ×1.25V
VOUT 2
=
(1+
R4
R3
)
×
0.86V
Eq.1
Eq.2
Layout Guide
A full GND plane without gap break.
VOUT1 to GND noise bypass – Short and wide
connection for C2 to Pin1 and Pin6.
VIN to GND noise bypass – Add a 100µF capacitor
close to L1 inductor, when VIN is not an idea
voltage source.
Minimized FB/LFB node copper area and keep far
away from noise sources.
Minimized parasitic capacitance connecting to LX
and EXT nodes, which may cause additional
switching loss.
The following diagram is an example of 2-layer
board layout for application circuits Fig.1 and
Fig.2.
First Layer
DS9264-00 December 2001
RT9264
Second Layer (Full GND Plane)
www.richtek-ic.com.tw
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