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PDF XC2C32A Data sheet ( Hoja de datos )
| Número de pieza | XC2C32A | |
| Descripción | CoolRunner-II CPLD | |
| Fabricantes | Xilinx | |
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R XC2C32A CoolRunner-II CPLD
DS310 (v2.1) November 6, 2008
0 0 Product Specification
Features
• Optimized for 1.8V systems
- As fast as 3.8 ns pin-to-pin logic delays
- As low as 12 μA quiescent current
• Industry’s best 0.18 micron CMOS CPLD
- Optimized architecture for effective logic synthesis
- Multi-voltage I/O operation: 1.5V through 3.3V
• Available in multiple package options
- 32-land QFN with 21 user I/Os
- 44-pin VQFP with 33 user I/Os
- 56-ball CP BGA with 33 user I/Os
- Pb-free available for all packages
• Advanced system features
- Fastest in system programming
· 1.8V ISP using IEEE 1532 (JTAG) interface
- IEEE1149.1 JTAG Boundary Scan Test
- Optional Schmitt-trigger input (per pin)
- Two separate I/O banks
- RealDigital 100% CMOS product term generation
- Flexible clocking modes
- Optional DualEDGE triggered registers
- Global signal options with macrocell control
· Multiple global clocks with phase selection per
macrocell
· Multiple global output enables
· Global set/reset
- Efficient control term clocks, output enables and
set/resets for each macrocell and shared across
function blocks
- Advanced design security
- Open-drain output option for Wired-OR and LED
drive
- Optional configurable grounds on unused I/Os
- Optional bus-hold, 3-state, or weak pullup on
selected I/O pins
- Mixed I/O voltages compatible with 1.5V, 1.8V,
2.5V, and 3.3V logic levels
- PLA architecture
· Superior pinout retention
· 100% product term routability across function
block
- Hot pluggable
Refer to the CoolRunner™-II family data sheet for the archi-
tecture description.
Description
The CoolRunner™-II 32-macrocell device is designed for
both high performance and low power applications. This
lends power savings to high-end communication equipment
and high speed to battery operated devices. Due to the low
power stand-by and dynamic operation, overall system reli-
ability is improved.
This device consists of two Function Blocks interconnected
by a low power Advanced Interconnect Matrix (AIM). The
AIM feeds 40 true and complement inputs to each Function
Block. The Function Blocks consist of a 40 by 56 P-term
PLA and 16 macrocells which contain numerous configura-
tion bits that allow for combinational or registered modes of
operation.
Additionally, these registers can be globally reset or preset
and configured as a D or T flip-flop or as a D latch. There
are also multiple clock signals, both global and local product
term types, configured on a per macrocell basis. Output pin
configurations include slew rate limit, bus hold, pull-up,
open drain, and programmable grounds. A Schmitt trigger
input is available on a per input pin basis. In addition to stor-
ing macrocell output states, the macrocell registers can be
configured as "direct input" registers to store signals directly
from input pins.
Clocking is available on a global or Function Block basis.
Three global clocks are available for all Function Blocks as a
synchronous clock source. Macrocell registers can be indi-
vidually configured to power up to the zero or one state. A
global set/reset control line is also available to asynchro-
nously set or reset selected registers during operation.
Additional local clock, synchronous clock-enable, asynchro-
nous set/reset, and output enable signals can be formed
using product terms on a per-macrocell or per-Function
Block basis.
The CoolRunner-II 32-macrocell CPLD is I/O compatible
with standard LVTTL and LVCMOS18, LVCMOS25, and
LVCMOS33 (see Table 1). This device is also 1.5V I/O com-
patible with the use of Schmitt-trigger inputs.
Another feature that eases voltage translation is I/O bank-
ing. Two I/O banks are available on the CoolRunner-II 32A
macrocell device that permit easy interfacing to 3.3V, 2.5V,
1.8V, and 1.5V devices.
© 2004–2008 Xilinx, Inc. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS310 (v2.1) November 6, 2008
Product Specification
www.xilinx.com
1
1 page  
R XC2C32A CoolRunner-II CPLD
Schmitt Trigger Input DC Voltage Specifications
Symbol
VCCIO
VT+
VT-
Parameter
Input source voltage
Input hysteresis threshold voltage
Test Conditions
Min.
1.4
0.5 x VCCIO
0.2 x VCCIO
Max.
3.9
0.8 x VCCIO
0.5 x VCCIO
Units
V
V
V
AC Electrical Characteristics Over Recommended Operating Conditions
-4 -6
Symbol
Parameter
Min. Max. Min. Max. Units
TPD1
Propagation delay single p-term
- 3.8 - 5.5 ns
TPD2
Propagation delay OR array
- 4.0 - 6.0 ns
TSUD
Direct input register clock setup time
1.7 - 2.2 - ns
TSU1
Setup time fast (single p-term)
1.9 - 2.6 - ns
TSU2
Setup time (OR array)
2.1 - 3.1 - ns
THD Direct input register hold time
0.0 - 0.0 - ns
TH P-term hold time
0.0 - 0.0 - ns
TCO
FTOGGLE(1)
FSYSTEM1(2)
Clock to output
Internal toggle rate
Maximum system frequency
- 3.7 - 4.7 ns
- 500 - 300 MHz
- 323 - 200 MHz
FSYSTEM2(2)
FEXT1(3)
FEXT2(3)
Maximum system frequency
Maximum external frequency
Maximum external frequency
- 303 - 182 MHz
- 179 - 137 MHz
- 172 - 128 MHz
TPSUD
Direct input register p-term clock setup time
0.4 - 0.9 - ns
TPSU1
P-term clock setup time (single p-term)
0.6 - 1.3 - ns
TPSU2
P-term clock setup time (OR array)
0.8 - 1.8 - ns
TPHD
Direct input register p-term clock hold time
1.5 - 1.6 - ns
TPH P-term clock hold
1.3 - 1.2 - ns
TPCO
P-term clock to output
- 5.0 - 6.0 ns
TOE/TOD
Global OE to output enable/disable
- 4.7 - 5.5 ns
TPOE/TPOD P-term OE to output enable/disable
- 6.2 - 6.7 ns
TMOE/TMOD Macrocell driven OE to output enable/disable
- 6.2 - 6.9 ns
TPAO
P-term set/reset to output valid
- 5.5 - 6.8 ns
TAO Global set/reset to output valid
- 4.5 - 5.5 ns
TSUEC
Register clock enable setup time
2.0 - 3.0 - ns
THEC
Register clock enable hold time
0.0 - 0.0 - ns
TCW
Global clock pulse width High or Low
1.4 - 2.2 - ns
TPCW
P-term pulse width High or Low
4.0 - 6.0 - ns
TAPRPW
TCONFIG(4)
Asynchronous preset/reset pulse width (High or Low)
Configuration time
4.0 - 6.0 - ns
- 50 - 50 μs
Notes:
1. FTOGGLE is the maximum clock frequency to which a T-Flip Flop can reliably toggle (see the CoolRunner-II family data sheet).
2.
FSYSTEM1
macrocell
w(1h/TileCYFCSLYES)TiEsMth2eisinthterronuaglhotpheeraOtinRgafrreraqyu.ency
for
a
device
fully
populated
with
one
16-bit
counter
through
one
p-term
per
3. FEXT1 (1/TSU1+TCO) is the maximum external frequency using one p-term while FEXT2 is through the OR array.
4. Typical configuration current during TCONFIG is 500 μA.
DS310 (v2.1) November 6, 2008
Product Specification
www.xilinx.com
5
5 Page 
R XC2C32A CoolRunner-II CPLD
I/O(1)
I/O(1)
I/O(1)
VAUX
I/O
I/O(2)
I/O(2)
I/O(2)
1
2
3
4
5
6
7
8
QFG32
Top View
24 I/O
23 I/O
22 Input
21 Gnd
20 Vcc
19 I/O
18 I/O
17 I/O
I/O(2)
1
I/O 2
I/O 3
GND
I/O
4
5
VQ44
I/O
VCCIO1
6
7
Top View
I/O 8
TDI 9
TMS 10
TCK 11
33 I/O(1)
32 I/O(1)
31 I/O(1)
30 I/O(3)
29 I/O
28 I/O
27 I/O
26 VCCIO2
25 GND
24 TDO
23 I/O
(1) - Global Output Enable
(2) - Global Clock
(3) - Global Set/Reset
Figure 6: QFG32 Package
(1) - Global Output Enable
(2) - Global Clock
(3) - Global Set/Reset
Figure 7: VQ44 Package
I/O(2)
7
I/O 8
I/O 9
GND
I/O
10
11
PC44
I/O 12 Top View
VCCIO1
13
I/O 14
TDI 15
TMS 16
TCK 17
39 I/O(1)
38 I/O(1)
37 I/O(1)
36 I/O(3)
35 I/O
34 I/O
33 I/O
32 VCCIO2
31 Gnd
30 TDO
29 I/O
(1) - Global Output Enable
(2) - Global Clock
(3) - Global Set/Reset
Figure 8: PC44 Package
DS310 (v2.1) November 6, 2008
Product Specification
www.xilinx.com
11
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet XC2C32A.PDF ] | |
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