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PDF PI3WVR31313A Data sheet ( Hoja de datos )
| Número de pieza | PI3WVR31313A | |
| Descripción | DP/HDMI 1:3 De-multiplexer switches | |
| Fabricantes | Pericom Semiconductor | |
| Logotipo |  |
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PI3WVR31313A
DP/HDMI 1:3 De-multiplexer switches
Features
ÎÎDP/HDMI 1:3 De-multiplexer switch with 4 high speed
differential channel and AUX/DDC, HPD and CAB_DET
signal channels
ÎÎTwo passive output ports for DP1.2 at5.4Gbps signals
ÎÎOne active output port with integrated DP to HDMI re-
driver (level shifter) supports HDMI 1.4 at 3.4Gbps
ÎÎPin control mode supports auto port priority selection
ÎÎPin control mode supports port3 with DDC bi-direction
buffer switch only
ÎÎI2C control mode supports auto port priority selection
ÎÎI2C control mode supports port3 with 8 levels equalization
and 5 levels pre-emphasis
ÎÎI2C control mode supports port3 with either DDC bi-
direction buffer switch or DDC passive switch
ÎÎVery low operating power when passive port1 and port2 are
selected
ÎÎ3.3V power supply
ÎÎ2KV HBM ESD protection for all I/O pins of port1, port2
and all control pins
ÎÎ8kV contact ESD (IEC61000-4-2) protection for all output
pins in port3
ÎÎPackaging:
60 pin TQFN package (5x9mm, 0.4mm pitch)
ÎÎSupport Type2 cable ID register
Description
PI3WVR31313A has two passive output port1 and port2, one ac-
tive (DP to HDMI) output port3. Passive output ports support
DP1.2 at 5.4Gbps. Active port3 support HDMI1.4b at 3.4Gbps.
All three output ports support auto port priority selection. In-
put port accepts DP1.2 and DP++ signals associated with output
ports as described above.
Application
ÎÎNotebook
Pin Configuration: TQFN-60
OEB
SCL
SDA
VDD
HPD_SRC
CAB_SRC
D0P
D0N
D1P
D1N
D2P
D2N
D3P
D3N
SDA_CTL/PRI_SEL
SCL_CTL/EQ
I2C_A1/PRE_EMP
I2C_A2/ROUT_SEL
HPD3
HPD2
60 59 58 57 56 55 54 53 52 51
1 50
2 49
3 48
4 47
5 46
6 45
7 44
8 43
9
Center Pad
42
10
11
12
TQFN-60
5x9 mm
41
40
39
13 38
14 37
15 36
16 35
17 34
18 33
19 32
20 31
21 22 23 24 25 26 27 28 29 30
VDD
D0P1
D0N1
D1P1
D1N1
D2P1
D2N1
D3P1
D3N1
D0P2
D0N2
D1P2
D1N2
D2P2
D2N2
D3P2
D3N2
CEXT
HPD1
MS
All trademarks are property of their respective owners.
15-0162
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1 page  
PI3W VR31313A
DP/HDMI 1:3 De-multiplexer switches
Pin mapping for dual mode DP source DEMUX to DP output
DP mode
ML_lane0(P)
ML_lane0(N)
ML_lane1(P)
ML_lane1(N)
ML_lane2(P)
ML_lane2(N)
ML_lane3(P)
ML_lane3(N)
HDMI/DVI mode
TX2+
TX2-
TX1+
TX1-
TX0+
TX0-
TXC+
TXC-
WVR31313A
input pins
D0P
D0N
D1P
D1N
D2P
D2N
D3P
D3N
WVR31313A
port1 output
D0P1
D0N1
D1P1
D1N1
D2P1
D2N1
D3P1
D3N1
WVR31313A
port2 output
D0P2
D0N2
D1P2
D1N2
D2P2
D2N2
D3P2
D3N2
WVR31313A
port3 output
D2P3
D2N3
D1P3
D1N3
D0P3
D0N3
CLKP3
CLKN3
Function Description
The MS pin selects I2C or pin control mode.
Pin control mode has only automatic port selection. I2C control mode has automatic port selection.
In auto port selection, when only one HPD high detected, the port with HPD high will be selected. When multiple HPD high
detected, the PRI_SEL pin(priority select) will determine the priority of the 3 ports.
When PRI_SEL=low, the port-priority will be port1-port2-port3 from high to low; when PRI_SEL=high, the port priority will be
port1-port3-port2 from high to low; when PRI_SEL=M (open as not connected), the port priority will be port3-port1-port2 from
high to low.
When port 1 (or port2) is selected and CAB_1 (or CAB_2) is low as in DP mode, the AUX/DDC channels will work as AUX
channels. AUXP shall have 100Kohm external resistor to GND and AUXN shall have 100Kohm external resistor to VDD. The data
rate of AUX channels will be >720Mbps.The internal DDC switch will be off.
When port 1 (or port2) is selected and CAB_1 (or CAB_2) is high when DP to HDMI adapter plugged, the AUX/DDC channels will
work as DDC channels. The internal DDC channels are on and the AUX channels are off. The input of DDC channels can tolerate
5V input and voltage of DDC to source will be limited about 3.3V or below.
When port 1 or port 2 is selected (passive ports), port3 with HDMI re-driver will shut down.
When port 3 is selected, the internal DP to HDMI level shifter will be enabled. There will be 3 EQ and 3 Pre-emphasis settings in
pin control mode, 8 EQ and 5 Pre-emphasis settings in I2C control mode.
When port 3 is selected, HDMI output can be standard TMDS-open-drain source, as well to be selected with internal source
termination as 50 ohm pull up to 3.3V VDD, using ROUT_SEL pin control or I2C control.
When port 3 is active as DP to HDMP level shifter, the DDC channel can be selected between bi-direction DDC buffer and passive
DDC switch.
HPD1, HPD2 and HPD3 are with internal CMOS buffers and can support 3.3V and 5V HPD inputs.
Squelch Mode
Squelch function will disable HDMI data output (as high impedance)when the voltage and frequency of input clock (TMDS) are
below squelch threshold, which will prevent random noise presenting in HDMI data output, thereby prevent noise on sink display.
Squelch function will enable-resume HDMI data output when input clock signals are above squelch threshold.
All trademarks are property of their respective owners.
15-0162
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5 Page 
PI3W VR31313A
DP/HDMI 1:3 De-multiplexer switches
Parameter
Description
Test Conditions
High Speed Channel Port3 (D[0:2]P3/N3, CLKP3/N3)
VI(open)
Single-ended input voltage under
high impedance input or open
input
IL=10uA
RT
Input termination resistance
VIN=2.9V
IOZ
Leakage current resistance
VDD=3.6V, OEB=High
Ioff
Power off leakage current
VDD=0, VIN=3.6V
Min. Typ. Max. Unit
VDD-10
VDD+10 mV
45 50 66 ohm
30 100 uA
-100 100 uA
Dynamic Electrical Characteristics over Operating Range
(TA = -40º to +105ºC, VDD = 3.3V ±10%)
Parameter Description
Test Conditions
TMDS Differential Pins
tpd
tr
tf
tsk(p)
tsk(D)
tsk(o)
Tjit_clk(pp)
Tjit_dat(pp)
ten
tdis
Propagation delay
Differential output signal rise time
(20% - 80%)
Differential output signal fall time
(20% - 80%)
Pulse skew
Intra-pair differential skew
Inter-pair differential skew(2)
Peak-to-peak output jitter CLK
residual jitter
Peak-to-peak output jitter DATA
Residual Jitter
Enable time
Disable time
VDD = 3.3V, Rout = 50Ω off, open
drain, 0dB pre-emphasis
Data Input = 3.4 Gbps HDMI data
pattern from signal generation,
short trace.
CLK Input = 340 MHz clock
when channel is active
SCL, SDA channel, AUX channel , CAB channel : passive switches
tpd(DDC)
Propagation delay from SCLn/
SDAn to SCL/SDA or SCL/SDA to
SCLn/SDAn In passive SW on.
CL = 10pF, in passive switch
SCL3, SDA3- SCL,SDA channel : buffers
tPLH LOW-to-HIGH propagation delay
tPHL HIGH-to-LOW propagation delay
tPLH LOW-to-HIGH propagation delay
tPHL HIGH-to-LOW propagation delay
SCL/SDA to SCL3/SDA3
SCL/SDA to SCL3/SDA3
SCL3/SDA3 to SCL/SDA
SCL3/SDA3 to SCL/SDA
Min.
50
10
50
10
Typ.
120
120
15
25
15
25
100
20
100
20
Max. Unit
2000
50 ps
50
100
40
50
10
50
us
5 ns
150 ns
40 ns
150 ns
40 ns
All trademarks are property of their respective owners.
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11 Page | ||
| Páginas | Total 27 Páginas | |
| PDF Descargar | [ Datasheet PI3WVR31313A.PDF ] | |
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