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PDF PI3WVR31212A Data sheet ( Hoja de datos )

Número de pieza PI3WVR31212A
Descripción DP/HDMI 1:2 De-multiplexer switches
Fabricantes Pericom Semiconductor 
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PI3WVR31212A
DP/HDMI 1:2 De-multiplexer switches
Features
ÎÎDP/HDMI 1:2 De-multiplexer switch with 4 high speed
differential channel and AUX/DDC, HPD and CAB_DET
signal channels
ÎÎOne passive output ports for DP1.2 at 5.4Gbps
ÎÎOne active output port with integrated DP to HDMI re-
driver (level shifter) supports HDMI 1.4 at 3.4Gbps
ÎÎPin control mode supports auto port priority selection
ÎÎPin control mode supports port2 with DDC bi-direction
buffer switch only
ÎÎI2C control mode supports auto port priority selection
ÎÎI2C control mode supports port2 with 8 levels equalization
and 5 levels pre-emphasis
ÎÎI2C control mode supports port2 with either DDC bi-
direction buffer switch or DDC passive switch
ÎÎVery low operating power when passive port1 is selected
ÎÎ3.3V power supply
ÎÎ2KV HBM ESD protection for all I/O pins of port1 and all
control pins
ÎÎ8kV contact ESD (IEC61000-4-2) protection for all output
pins in port2
ÎÎPackaging:
60 pin TQFN package (5x9mm, 0.4mm pitch)
ÎÎSupport Type 2 cable ID register
Description
PI3WVR31212A has one passive output port1, one active (DP to
HDMI) output port2. Passive output supports DP1.2 at 5.4Gbps
in I2C mode. Active port2 supports HDMI1.4b at 3.4Gbps.All
two output ports support auto port priority selection. Input port
accepts DP1.2 and DP++ signals associated with output ports as
described above.
Application
ÎÎNotebook and dongle
Pin Configuration: TQFN-60
OEB
SCL
SDA
VDD
HPD_SRC
CAB_SRC
D0P
D0N
D1P
D1N
D2P
D2N
D3P
D3N
SDA_CTL/PRI_SEL
SCL_CTL/EQ
I2C_A1/PRE_EMP
I2C_A2/ROUT_SEL
HPD2
GND
60 59 58 57 56 55 54 53 52 51
1 50
2 49
3 48
4 47
5 46
6 45
7 44
8 43
9
Center Pad
42
10
11
12
TQFN-60
5x9 mm
41
40
39
13 38
14 37
15 36
16 35
17 34
18 33
19 32
20 31
21 22 23 24 25 26 27 28 29 30
VDD
D0P1
D0N1
D1P1
D1N1
D2P1
D2N1
D3P1
D3N1
GND
NC
NC
NC
GND
NC
NC
GND
CEXT
HPD1
MS
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PI3WVR31212A pdf
PI3W VR31212A
DP/HDMI 1:2 De-multiplexer switches
Pin mapping for dual mode DP source DEMUX to DP output
DP mode
ML_lan0(P)
ML_lan0(N)
ML_lan1(P)
ML_lan1(N)
ML_lan2(P)
ML_lan2(N)
ML_lan3(P)
ML_lan3(N)
HDMI/DVI mode
TX2+
TX2-
TX1+
TX1-
TX0+
TX0-
TXC+
TXC-
WVR31212A input pins
D0P
D0N
D1P
D1N
D2P
D2N
D3P
D3N
WVR31212A port1 output
D0P1
D0N1
D1P1
D1N1
D2P1
D2N1
D3P1
D3N1
WVR31212A port2 output
D2P2
D2N2
D1P2
D1N2
D0P2
D0N2
CLKP2
CLKN2
Function Description
The MS pin selects I2C or pin control mode.
Pin control mode has only automatic port selection. I2C control mode has automatic port selection.
In auto port selection, when only one HPD high detected, the port with HPD high will be selected. When multiple HPD high detected,
the PRI_SEL pin (priority select) will determine the priority of the 2 ports. See priority selection table
When PRI_SEL=low or High, the port-priority will be port1-port2 from high to low; when PRI_SEL=M (open as not connected), the
port priority will be port2-por1 from high to low.
When port 1 is selected and CAB_1 is low as in DP mode, the AUX/DDC channels will work as AUX channels. AUXP shall have
100Kohm external resistor to GND and AUXN shall have 100Kohm external resistor to VDD. The data rate of AUX channels will be
>720Mbps.The internal DDC switch will be off.
When port 1 is selected and CAB_1 is high when DP to HDMI adapter plugged, the AUX/DDC channels will work as DDC channels.
The internal DDC channels are on and the AUX channels are off. The input of DDC channels can tolerate 5V input and voltage of
DDC to source will be limited about 3.3V or below.
When port 1 is selected (passive ports), port2 with HDMI re-driver will shut down.
When port 2 is selected, the internal DP to HDMI level shifter will be enabled. There will be 3 EQ and 3 Pre-emphasis settings in pin
control mode, 8 EQ and 5 Pre-emphasis settings in I2C control mode.
When port 2 is selected, HDMI output can be standard TMDS-open-drain source, as well to be selected with internal source termina-
tion as 50 ohm pull up to 3.3V VDD, using ROUT_SEL pin control or I2C control.
When port 2 is active as DP to HDMP level shifter, the DDC channel can be selected between bi-direction DDC buffer and passive
DDC switch in I2C mode.
HPD1, HPD2 are with internal CMOS buffers and can support 3.3V and 5V HPD inputs.
Squelch Mode
Squelch function will disable HDMI data output (as high impedance)when the voltage and frequency of input clock (TMDS) are
below squelch threshold, which will prevent random noise presenting in HDMI data output, thereby prevent noise on sink display.
Squelch function will enable-resume HDMI data output when input clock signals are above squelch threshold.
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PI3WVR31212A arduino
PI3W VR31212A
DP/HDMI 1:2 De-multiplexer switches
Parameter Description
Control and Status Pins (HPDn, HPD_SRC)
tpd(HPD)
Propagation delay (from HPDx to
the active port of HPD_SRC, high
to low)
tsx(HPD)
Switch time (from port select to
the latest HPD , manual selection
mode)
Test Conditions
CL = 10pF
Dynamic Electrical Characteristics
Parameter Description
Test Conditions
High Speed Channel (D[0:3]P/N – D[0:3]P1/N1)
XTALK
Crosstalk on High Speed Channels
OIRR
ILOSS
Rloss
BW_Dx±
BW_AUX
Tstartup
Twakeup
Tpd
tb-b
tch-ch
OFF Isolation on High Speed
Channels
Differential Insertion Loss on
High Speed Channels
Differential Return Loss on High
Speed Channels
Bandwidth -3dB for Main high
speed path (Dx±)
Bandwidth -3dB for AUX
VDD valid to channel enable
Enabling output by changing OEB
from High to Low
Propagation delay (input pin to
output pin) on all channels
Bit-to-bit skew within the same
differential pair of Dx± channels
Channel-to-channel skew of Dx±
channels
See Fig. 1 for
Measurement
Setup
See Fig. 2 for
Measurement
Setup
f= 2.7 GHz
f= 2.7 GHz
@2.7GHZ (see figure 3)
@ 2.7GHz (5.4Gbps)
See figure 3
See figure 3
Min. Typ. Max. Unit
2 4 us
2 4 us
Min. Typ. Max. Unit
-32 -30
-19 -17 dB
-1.7 -1.5
dB
-18.0 -16.0 dB
5.1 5.6
1.2 1.5
250
250
GHz
GHz
us
us
80 ps
5 7 ps
35 ps
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