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PDF 24NM65N Data sheet ( Hoja de datos )

Número de pieza 24NM65N
Descripción N-channel Power MOSFET
Fabricantes STMicroelectronics 
Logotipo STMicroelectronics Logotipo



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No Preview Available ! 24NM65N Hoja de datos, Descripción, Manual

STW24NM65N-STI24NM65N-STF24NM65N
STB24NM65N - STP24NM65N
N-channel 650 V - 0.16 - 19 A - TO-220 - TO-220FP - D2PAK
I2PAK - TO-247 second generation MDmesh™ Power MOSFET
Features
Type
STB24NM65N
STI24NM65N
STF24NM65N
STP24NM65N
STW24NM65N
VDSS
(@TJmax)
710 V
710 V
710 V
710 V
710 V
RDS(on) max
< 0.19
< 0.19
< 0.19
< 0.19
< 0.19
ID
19 A
19 A
19 A(1)
19 A
19 A
1. Limited only by maximum temperature allowed
100% avalanche tested
Low input capacitance and gate charge
Low gate input resistance
Application
Switching applications
Description
This series of devices is designed using the
second generation of MDmesh™ technology. This
revolutionary Power MOSFET associates a new
vertical structure to the company’s strip layout to
yield one of the world’s lowest on-resistance and
gate charge. It is therefore suitable for the most
demanding high efficiency converters.
3
2
1
TO-220
3
2
1
TO-220FP
3
1
D²PAK
123
I²PAK
3
2
1
TO-247
Figure 1. Internal schematic diagram
Table 1. Device summary
Order codes
STB24NM65N
STI24NM65N
STF24NM65N
STP24NM65N
STW24NM65N
Marking
24NM65N
24NM65N
24NM65N
24NM65N
24NM65N
Package
D²PAK
I²PAK
TO-220FP
TO-220
TO-247
Packaging
Tape and reel
Tube
Tube
Tube
Tube
February 2008
Rev 1
1/19
www.st.com
19

1 page




24NM65N pdf
STB24NM65N-STI24NM65N-STF24NM65N-STP/W24NM65N
2 Electrical characteristics
Electrical characteristics
(TCASE=25 °C unless otherwise specified)
Table 5. On/off states
Symbol
Parameter
Test conditions
Min. Typ. Max. Unit
Drain-source
V(BR)DSS breakdown voltage
dv/dt (1) Drain source voltage slope
IDSS
IGSS
VGS(th)
RDS(on)
Zero gate voltage
drain current (VGS = 0)
Gate-body leakage
current (VDS = 0)
Gate threshold voltage
Static drain-source on
resistance
ID = 1 mA, VGS = 0
650
VDD= 520 V, ID=19 A,
VGS=10 V
VDS = max rating
VDS = max rating, @125 °C
VGS = ± 20 V
VDS = VGS, ID = 250 µA
2
VGS = 10 V, ID = 9.5 A
V
35 V/ns
1 µA
100 µA
±100 nA
34
0.16 0.19
V
1. Characteristic value at turn off on inductive load
Table 6. Dynamic
Symbol
Parameter
Test conditions
Min. Typ. Max. Unit
gfs (1)
Ciss
Coss
Crss
Forward transconductance
Input capacitance
Output capacitance
Reverse transfer
capacitance
VDS= 15 V, ID = 9.5 A
VDS = 50 V, f = 1 MHz,
VGS = 0
14
2500
120
10
S
pF
pF
pF
Coss
(2)
eq
Equivalent output
capacitance
VGS = 0, VDS = 0 to 520 V
310
pF
Qg Total gate charge
Qgs Gate-source charge
Qgd Gate-drain charge
VDD = 520 V, ID = 19 A,
VGS = 10 V,
(see Figure 19)
70 nC
10 nC
40 nC
RG Gate input resistance
f=1 MHz gate DC bias = 0
Test signal level = 20 mV
open drain
2.5
1. Pulsed: pulse duration = 300µs, duty cycle 1.5%
2. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS
increases from 0 to 80% VDSS
5/19

5 Page





24NM65N arduino
STB24NM65N-STI24NM65N-STF24NM65N-STP/W24NM65N
4 Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect. The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com
11/19

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