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PDF GC5016 Data sheet ( Hoja de datos )
| Número de pieza | GC5016 | |
| Descripción | Wideband Quad Digital Down-Converter/Up-Converter (Rev. J) | |
| Fabricantes | Texas | |
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GC5016
SLWS142G − JANUARY 2003 − REVISED NOVEMBER 2005
WIDEBAND QUAD DIGITAL DOWNĆCONVERTER/UPĆCONVERTER
FEATURES
D Four Independently Configurable Wideband
Down-Converter or Up-Converter Channels
− Four Channel Down Convert Mode
− Four Channel Up Convert Mode
− Two Channels Down and Two Channels
Up Mode
D Down-Conversion Channel Mode
− Input Rates to 160-MSPS for Four
Channels, 320-MSPS for Two Channels in
Double Rate Mode
− Four Wideband Down-Conversion
Channels Support UMTS Standards
− 115-dB SFDR
− FIR Filter Block Consists of 16 Cells
Providing Up to 256 Taps Per Channel
− 64 Parallel Input Bits and 64 Parallel
Output Bits Provide Flexible I/O Options
− Many Multiplex Output Options
D Up-Conversion Channel Mode
− Output Rates to 160-MSPS for Four
Channels, 320-MSPS for Two Channels
− Four Up-Conversion Channels Support
UMTS Standards
− FIR Filter Block Consists of 16 Cells
Providing up to 256 Taps Per Channel
− 64 Parallel Input Bits and 64 Parallel
Output Bits Provide Flexible I/O Options
− Multiple Real and Complex Outputs
− Two Channel Double Rate Real Output
Mode With Rates to 320 MSPS
− Outputs Can Be Independent, Summed
Into Two or One Output(s), and Optionally
Merged With Multiple GC5016 Chips
D JTAG Boundary Scan
D 3.3-V I/O, 1.8-V Core
D Power Dissipation: <1 W for Four Channels
D Package: 252-Ball, 17-mm PBGA, 1-mm Pitch
APPLICATIONS
D Cellular Base Transceiver Station Transmit
and Receive Channels
− WCDMA
− CDMA2000
D Radar
D General Filtering
D Test and Measurement
Table of Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 12 Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 13 GC5016 Down-Conversion Mode . . . . . . . . . . . . . . . . . . . . . . . 11
3 Other Reference Material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 14 GC5016 Up-Conversion Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 15 GC5016 in Transceiver Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
5 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . 3 16 General GC5016 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
6 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 17 Configuration Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
7 AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 18 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
8 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 19 Board Bring-Up Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
9 Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
10 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
11 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products
conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters.
Copyright 2003 − 2005, Texas Instruments Incorporated
1 page  
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9 POWER CONSUMPTION
GC5016
SLWS142G − JANUARY 2003 − REVISED NOVEMBER 2005
The maximum power consumption depends on the operating mode of the chip. The following equation estimates the
typical power supply current for the chip. Chip-to-chip variation is typically ±5%. The AC Characteristics provides the
production test limit for current in a maximum configuration. It is 10% over the typical value.
Icore = (fCK/100 MHz) (Vcore/1.8 V) (Number_of_Active_Channels/4) (0.75 + FIRDutyCycle) 220 mA
The FIRDutyCycle is calculated in the cmd5016 programming software. The ’.ANL’ extension of the user
programming file contains the power analysis value.. It can be estimated by:
Down Converter Mode:
FIRDutyCycle = 1 for fCK/Fout ≤ 16
16 x Fout/fCK otherwise
Up Converter Mode:
FIRDutyCycle = 1 for fCK/Fin ≤ 32
32 x Fin/fCK otherwise
Current consumption on the pad supply is primarily due to the external loads and follows C x V x F. Internal loads
are estimated at 2 pF per pin. Data outputs transition from a zero to a one once per four clocks, while clock outputs
transition every cycle. The frame strobes consume negligible power due to the low transition frequency. In general:
Ipad = Σ DataPad/4 x C x F x V + Σ ClockPad x C x F x V
Typically loads are 20 pF per pin. A worst case current would be all four output ports operating at 125 MHz and the
four output clocks with [A−D]CK active at 125 MHz.
Ipad = (64/4 + 4) x (C+2pF) x Fout x Vpad = 20 x 22 pF x 125 MHz x 3.3 V = 180 mA
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GC5016
SLWS142G − JANUARY 2003 − REVISED NOVEMBER 2005
SIGNAL TYPE
DESCRIPTION
DATA I/O (CONTINUED)
IFLG
O Clocked output A flag used to indicate which samples are real or imaginary in up-conversion mode when I and Q are time
multiplexed.
WRMODE I A static control input that changes the timing of control writes. Normally tied low. When low control write data must be
stable for a setup time ahead and hold time after the end of the write strobe. When high data must be stable for a setup
time ahead of the write strobe going active until a hold time after it goes inactive.
RST
I Chip reset bar. Active low signal. Not clocked. RST requires an external pull-up resistor or connection to VCOR Power
Monitor “1” is OK.
SIA I Sync input A bar. Active low data input signal. SIA requires an external pull-up resistor if not used.
SIB I Sync input B bar. Active low data input signal. SIB requires an external pull-up resistor if not used.
SO O Sync output bar. Active low data output signal
JTAG I/O
TCK
I JTAG clock – Active high input. Internal pullup
TDI I JTAG data in – Active high input clocked on TCK rising. Internal pullup
TDO
O JTAG data out – High-impedance state output clocked on falling edge of TCK.
TMS
I JTAG interface – Active high input clocked on TCK rising. Internal pullup
TRST
I Asynchronous JTAG reset bar. Internal pullup
SUPPLIES
GND
Ground
VCOR(1)
Core supply voltage. Used to supply the core logic, nominally set to 1.8 V.
VPAD(1)
Interface voltage. Used to set the I/O levels for all pins, nominally set at 3.3 V.
(1) The VCore and VPad must both be powered before programming the GC5016 Control Bus. There is no required power sequence.
The recommendation is to power VCore before or simultaneously with VPad.
13 GC5016 DOWN-CONVERSION MODE
13.1 Overview
Figure 1 shows the functional block diagram for the GC5016 when configured as a 4-channel digital
down-converter(DDC). In a common configuration, each down-conversion channel demodulates ADC sampled data
down from an IF frequency to 0Hz, low pass filters the signal data, reduces the signal rate (decimation), and outputs
I and Q baseband data. The baseband signal is measured by the Power Meter, and a gain or gain + automatic gain
are applied to the IQ data. Several output formats are available for transmitting the IQ outputs.
The DDC input can be configured for real or complex inputs. The input data on ports AI[15..0], BI[15..0], CI[15..0],
are converted to a complex input format in the Receive Input Formatter (RINF).
The Mixer stage provides the Receive Input channel selection (RSEL), digital oscillator (NCO), and complex mixing
logic (mixer) to translate the input down to 0 Hz.
After the Mixer, the 5 stage Cascade Integrator Comb (CIC) provides complex filtering and decimation. The CIC
decimation is an integer value from 1 to 256. Special logic is used for double rate processing.
After the CIC complex filter, the Programmable Finite Impulse Response (PFIR) filter provides CIC correction,
spectral shaping, and further decimation. The PFIR decimates from 1 to 16.
The PFIR complex output is measured by the Complex Power Meter. The Power Meter integrates the IQ power. The
time integrated value can be read through the Microprocessor port.
The PFIR complex output is gain (manual + adaptive) scaled.An automatic gain (adaptive gain) is computed based
on the current IQ output level. The gain scaled output is rounded to a desired number of bits resolution, and is
formatted for the DDC output.
Channels can be synchronized to support beam forming or frequency hopped systems. Two channels can be
operated in tandem to allow double input bandwidth, double output bandwidth, or both.
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet GC5016.PDF ] | |
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