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PDF TC9328AF Data sheet ( Hoja de datos )

Número de pieza TC9328AF
Descripción Portable Audio DTS Controller
Fabricantes Toshiba 
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No Preview Available ! TC9328AF Hoja de datos, Descripción, Manual

TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC9328AF
Portable Audio DTS Controller (DTS-21)
TC9328AF
The TC9328AF is a single-chip DTS microcontroller for
portable audio incorporating 230 MHz prescaller, PLL, and LCD
driver. In addition to a 20-bit IF counter, 6-bit A/D converter,
serial interface, and buzzer function, the device supports an
interrupt function, 8-bit timer/counter, and 8-bit pulse counter.
The LCD driver features built-in 1/4 duty, 1/2 bias and a 3 V
voltage doubler boosting circuit, implementing stable LCD.
The power supply voltage ranges from 0.9 to 1.8 V. Because of
its low-current consumption (CPU: 80 µA (max)), the device is
suitable for use in digital tuning systems in portable equipment
such as headphone stereos.
Features
Weight: 0.45 g (typ.)
CMOS DTS microcontroller LSI with built-in 230 MHz prescaller, PLL, and LCD driver
Operating voltage: VDD = 0.9 to 1.8 V (typ.: 1.5 V)
Current dissipation:
When CPU in operation: IDD = 40 µA (typ.)
When PLL in operation: IDD = 6 mA (typ.) (VHF mode)
Operating temperature range: Ta = 10 to 60°C
Program memory (ROM): 16-bit × 8192 steps
Data memory (RAM): 4-bit × 512 words
Instruction execution time: 40 µs
Crystal oscillator frequency: 75 kHz
Stack level: 8
General-purpose IF counter: 20-bit (CMOS input supported)
A/D converter: 6-bit × 4 channel
LCD driver: 1/4 duty, 1/2 bias, 88 segments (max)
I/O port: CMOS I/O ports: 12
N-channel open drain I/O ports: 24 (max)
Output-only port: 1
Input-only ports: 5 (max)
Timer/counter: 8-bit (as timer clock: INTR1/INTR2, instruction cycle: 1 kHz selectable)
Pulse counter: 8-bit up/down counter (input via INTR2 pin)
Buzzer: Built-in four mode: 0.625 to 3 kHz (8 types), Continuous, Single-Shot,
10 Hz Intermittent, or 10 Hz Intermittent 1 Hz Interval
Package: QFP-80 (0.5 mm pitch, 1.4 mm thick)
1 2004-09-13

1 page




TC9328AF pdf
Pin No. Symbol
Pin Name
Function and Operation
TC9328AF
Remarks
32~34 P2-0~P2-2 I/O port 2
I/O port 2
35 P2-3/PSC /Prescaller
/PSC output
The input and output of these 4-bit I/O
ports can be programmed in 1-bit units.
The P2-3 pin is also used as a PLL
prescaller PSC signal output pin. A PLL
can be configured using an external
prescaller. In such a case, set the pin to
I/O port output.
54~57
58~61
62~69
P3-0~P3-3
P5-0/ADin1~
P5-3/ADin4
P6-0~P7-3
4-bit I/O ports, allowing input and output
to be programmed in 1 bit units.
I/O port 3
I/O port 5
/AD analog voltage
input
I/O port 6, 7
Pins P5-0 to P5-3 can also be used for
analog input to the built-in 6-bit,
4-channel AD converter.
The conversion time of the built-in AD
converter using the successive
comparison method is 280 µs. The
necessary pin can be programmed to
AD analog input in 1-bit units. Up to the
doubled voltage VDB (VDD × 2) can be
input as the AD input voltage.
The I/O ports are N-ch open drain
output. Up to the VDB voltage can be
applied to the AD input pins, and up to
3.6 V can be applied to the I/O port
pins. I/O port 3 can obtain N-ch
high-output current (2 mA typ.) even at
low voltage.
The AD converter and all associated
controls are performed via sortware.
VLCD
VDD
Input
instruction
To AD converter
VDD
Input
instruction
5 2004-09-13

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TC9328AF arduino
TC9328AF
Pin No. Symbol
Pin Name
Function and Operation
Remarks
74 VDB
75 C1
76 C2
77 VEE
78 C3
79 C4
80 VLCD
Voltage doubler
boosting output
pins
Voltage doubler boosting output pins.
The VDB pin doubles the VDD pin
voltage using the voltage doubler
boosting capacitor between C1 and C2.
The doubled voltage is used for the AD
converter and constant voltage circuit
(Vreg, VEE) power supply.
The VEE pin supplies a constant
voltage of 1.5 V from the VDB voltage.
The voltage is doubled (to 3 V) using
the voltage doubler boosting capacitor
between C3 and C4. The doubled
voltage is then supplied to the VLCD
pin. The VEE potential and the VLCD
potential are used to drive the LCD.
Connect a stabilizing capacitor between
the VDB pin and GND (0.1 µF, 10 µF
typ.), and between the VLCD pin and
GND (0.1 µF typ.). Connect a voltage
doubler boosting capacitor (0.1 µF typ.)
between C1 and C2, and between C3
and C4. (Note 1)
VLCD
Note 1: When the LCD pin is set as an output port, the “H” level output is the doubled voltage VLCD. Therefore,
disconnect the voltage doubler boosting capacitor but connect the VLCD pin to the VDD pin.
11 2004-09-13

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