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PDF TC9327BFG Data sheet ( Hoja de datos )
| Número de pieza | TC9327BFG | |
| Descripción | DTS Microcontroller | |
| Fabricantes | Toshiba | |
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TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC9327BFG
TC9327BFG
DTS Microcontroller (DTS-21)
The TC9327BFG is a 4-bit CMOS microcontroller for
single-chip digital tuning systems, featuring a built-in 230-MHz
prescaler, PLL, and LCD drivers.
The CPU has 4-bit parallel addition and subtraction
instructions (e.g., AI, SI), logic operation instructions (e.g., OR,
AN), composite decision and comparison instructions (e.g., TM,
SL), and time-base functions.
The package is an 80-pin, 0.5 mm-pitch compact package. In
addition to various input/output ports and a dedicated key-input
port, which are controlled by powerful input/output instructions
(IN1 to 3, OUT1 to 3), there are many dedicated LCD pins, a
PWM output port, a BUZR port, a 6-bit A/D converter, a serial
interface, and an IF counter, etc.
Low-voltage and low-current consumption make this
microcontroller suitable for portable DTS equipment.
Weight: 0.45 g (typ.)
Features
• 4 bit microcontroller for single-chip digital tuning systems.
• Operating voltage VDD = 1.8 to 3.6 V, with low current consumption due to CMOS circuitry
(with only the CPU operating when VDD = 3 V, IDD = 100 µA max)
• Built-in prescaler (1/2 fixed divider +2 modulus prescaler: fmax ≥ 230 MHz)
• Features built-in 1/4-duty, 1/2-bias LCD drivers and a built-in 3 V booster circuit for the display.
• Data memory (RAM) and ports are easily backed up.
• Program memory (ROM): 16 bit × 7168 steps
• Data memory (RAM): 4 bit × 256 words
• 62-instruction set (all one-word instructions)
• Instruction execution time: 40 µs (with 75-kHz crystal) (MVGS, DAL instructions: 80 µs)
• Many addition and subtraction instructions (12 types each addition and subtraction)
• Powerful composite decision instructions (TMTR, TMFR, TMT, TMF, TMTN, TMFN)
• Data can be transmitted between addresses on the same row.
• Register indirect transfer available (MVGD, MVGS instructions).
• 16 powerful general registers (located in RAM)
• Stack levels: 2
• Free branching (JUMP instructions) is allowed in the 7168 steps of program memory (ROM) as there are no
pages or fields.
• 16 bits of any address in the 1024 program memory steps (ROM) can be referenced (DAL instructions).
• Features independent frequency input pins (FMIN and AMIN) and two (DO1 and DO2) phase comparator
outputs for FM/VHF and AM.
• Seven kinds of reference frequencies can be selected via software.
• Powerful input/output instructions (IN1 to 3, OUT1 to 3).
• Dedicated input ports (K0 to K3) for key input, 29 LCD drive pins (100 segments maximum) available.
• 29 I/O ports: 27 input/output programmable in 1-bit units, 1 output-only port, and 1 input-only port. The 2 IFIN,
and DO1 pins can be switched by instruction to IN1 (input-only) or OT2 (output-only). In addition, 9 output
LCD output pins for S17 to S25 can be switched to I/O port in 1-bit units.
• Three backup modes available by instruction: Only CPU operation, crystal oscillation only, clock stop.
• Features a built-in 2-Hz timer F/F and a built-in 10/100 Hz interval pulse outputs (internal port for time base).
1 2005-04-20
1 page  
Pin No. Symbol
Pin Name
Function and Operation
38~41 P1-0~P1-3
P2-0/ADIN1
42~45
P2-1/ADIN2
P2-2/ADIN3
P2-3/
DC-REF
46~49
P3-0/SI
P3-1/SO
P3 - 2/SCK
P3-3/BUZR
I/O port 1
I/O port 2
/AD analog voltage
input
/AD analog voltage
input
/AD analog voltage
input
/Reference voltage
input
I/O port 3
/Serial data input
/Serial data output
/Serial clock I/O
/Buzzer output
The input and output of these 4-bit I/O ports can
be programmed in 1-bit units. This pin is capable
of outputting timing signals for the key matrix by
program.
It contains load resistance in N-ch, and can form
the matrix for a push-key needing no diode for the
key matrix.
By altering the input of I/O ports set to input, the
CLOCK STOP mode or the WAIT mode can be
released, and the MUTE bit of the MUTE pin can
be set to “1”.
4-bit I/O ports, allowing input and output to be
programmed in 1-bit units.
Pins P2-0 to P2-2 can also be used for analog
input to the built-in 6-bit, 3-channel A/D converter.
The conversion time of the built-in A/D converter
using the successive comparison method is 280
µs. The necessary pin can be programmed to AD
analog input in 1-bit units, and P2-3 can be set to
the reference voltage input. Internal power supply
(VDD) or constant voltage (VEE) can be used as
the reference voltage. So battery voltage, etc., can
be easily detected. The reference voltage input,
for which a built-in operational amp. is used, has
high impedance.
The A/D converter and all associated controls are
performed via sortware.
4-bit I/O ports, allowing input and output to be
programmed in 1-bit units. Pins P3-0 to P3-2 can
also be used for the I/O terminals of serial
interface circuits (SIO).
SIO functions for 4-bit or 8-bit serial data inputs
from the SI pin and outputs from the SO pin at the
SCK pin clock edge.
The clock for serial operation ( SCK ) is capable of
internal/external options and rise/fall shift options.
The SO pin is also capable of switching to serial
inputs (SI), facilitating the control of various LSI’s
and communication between controllers. All SIO
inputs use built-in Schmitt circuits.
P3-3 pins also functions as the output for a built-in
buzzer. The buzzer output can select 8 kinds of
0.625 to 3 kHz frequencies with 4 modes:
continuous output, single-shot output, 10-Hz
intermittent output, and 10-Hz intermittent 1-Hz
interval output.
SIO, buzzer, and all associated controls can be
programmed.
50~61
P4 - 0/PWM
P4-1~
P6-2/CTRIN1
P6-3/CTRIN2
I/O port 4
/PWM output
I/O port 4~
I/O port 6
/Counter input
16-bit I/O ports, allowing input and output to be
programmed in 1-bit units.
The P4-0 pin is also used for built-in 12-bit PWM
outputs. The PWM outputs pulse continuously at
73.26 Hz, and can change the duty of the pulses
to 256 steps (8 bits), causing the added pulses to
be output using 4 bits for 16 cycles (218.5 ms).
The P6-2 and P6-3 pins are also used for input
purposes when using 20-bit IF counters as 12-bit
and 8-bit binary counters.
The P6-2 pin can be used for 12-bit binary counter
inputs, and the P6-3 pin for 8-bit binary counter
inputs.
PWM outputs, counter inputs, and all associated
controls can be programmed.
5
TC9327BFG
Remarks
2005-04-20
5 Page 
TC9327BFG
5. Data Memory (RAM)
The data memory consists of 4 bits × 256 words and is used for storing data. These 256 words are
expressed in row addresses (4 bits) and column addresses (4 bits). 192 words (row address = addresses 4H
to FH) within the data memory are addressed indirectly by the G-register. Owing to this, it is necessary to
specify the row address with the G-register before the data in this area can be processed.
The addresses 00H to 0FH within the data memory are known as general registers, and these can be
used simply by specifying the relevant column addresses (4 bit). These sixteen general registers can be
used for operations and transfers with the data memory, and may also be used as normal data memories.
Note 7: The column address (4 bit) that specifies the general register is the register number of the general
register.
Note 8: All row addresses (addresses 0H to FH) can be specified indirectly with the G-register.
Note 9: The indirect specification of row addresses = 0H to FH is also possible
6. G-Register (G-REG)
The G-register is a 4 bit register used for addressing the row addresses (DR = 4H to FH addresses) of the
data memory’s 192 words.
The contents of this register are validated when the MVGD instruction or MVGS instruction are
executed, and are not affected through the execution of any other instructions. This register is used as one
of the ports, and the contents are set when the OUT1 instruction from amongst the I/O instructions is
executed. (→ refer to section #1 in register ports.)
7. Data Register (DATA REG)
The data register consists of 1 × 16 bits and loads 16 bits of optional address data from amongst
addresses 000H to 3FFH in the program memory when the DAL instruction is executed. This register is
used as one of the ports, and the contents are loaded into the data memory in units of 4 bits when the IN1
instruction from amongst the I/O instructions is executed. (→ refer to section #2 in register ports.)
8. Carry F/F (CF/F)
This is set when either CARRY or BORROW are issued in the result of calculation instruction execution
and is reset if neither of these are issued.
The contents of carry F/F can only be amended through the execution of addition or subtraction
instructions and are not affected by the execution of any other instruction.
11 2005-04-20
11 Page | ||
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| PDF Descargar | [ Datasheet TC9327BFG.PDF ] | |
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