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PDF W631GG6KB Data sheet ( Hoja de datos )

Número de pieza W631GG6KB
Descripción 8M x 8 BANKS x 16-BIT DDR3 SDRAM
Fabricantes Winbond 
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W631GG6KB
8M 8 BANKS 16 BIT DDR3 SDRAM
Table of Contents-
1. GENERAL DESCRIPTION ...................................................................................................................5
2. FEATURES ...........................................................................................................................................5
3. ORDER INFORMATION .......................................................................................................................6
4. KEY PARAMETERS .............................................................................................................................7
5. BALL CONFIGURATION ......................................................................................................................8
6. BALL DESCRIPTION............................................................................................................................9
7. FUNCTIONAL DESCRIPTION............................................................................................................11
7.1 Basic Functionality ..............................................................................................................................11
7.2 RESET and Initialization Procedure ....................................................................................................11
7.2.1
Power-up Initialization Sequence .....................................................................................11
7.2.2
Reset Initialization with Stable Power ..............................................................................13
7.3 Programming the Mode Registers.......................................................................................................14
7.3.1
Mode Register MR0 .........................................................................................................16
7.3.1.1
Burst Length, Type and Order ................................................................................17
7.3.1.2
CAS Latency...........................................................................................................17
7.3.1.3
Test Mode...............................................................................................................18
7.3.1.4
DLL Reset...............................................................................................................18
7.3.1.5
Write Recovery .......................................................................................................18
7.3.1.6
Precharge PD DLL .................................................................................................18
7.3.2
Mode Register MR1 .........................................................................................................19
7.3.2.1
DLL Enable/Disable................................................................................................19
7.3.2.2
Output Driver Impedance Control ...........................................................................20
7.3.2.3
ODT RTT Values ....................................................................................................20
7.3.2.4
Additive Latency (AL) .............................................................................................20
7.3.2.5
Write leveling ..........................................................................................................20
7.3.2.6
Output Disable........................................................................................................20
7.3.3
Mode Register MR2 .........................................................................................................21
7.3.3.1
Partial Array Self Refresh (PASR) ..........................................................................22
7.3.3.2
CAS Write Latency (CWL) ......................................................................................22
7.3.3.3
Auto Self Refresh (ASR) and Self Refresh Temperature (SRT) .............................22
7.3.3.4
Dynamic ODT (Rtt_WR) .........................................................................................22
7.3.4
Mode Register MR3 .........................................................................................................23
7.3.4.1
Multi Purpose Register (MPR) ................................................................................23
7.4 No OPeration (NOP) Command..........................................................................................................24
7.5 Deselect Command.............................................................................................................................24
7.6 DLL-off Mode ......................................................................................................................................24
7.7 DLL on/off switching procedure...........................................................................................................25
7.7.1
DLL ―on‖ to DLL ―off‖ Procedure.......................................................................................25
Publication Release Date: Feb. 27, 2013
Revision A04
-1-

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W631GG6KB pdf
W631GG6KB
1. GENERAL DESCRIPTION
The W631GG6KB is a 1G bits DDR3 SDRAM, organized as 8,388,608 words 8 banks 16 bits. This
device achieves high speed transfer rates up to 1866 Mb/sec/pin (DDR3-1866) for various
applications. W631GG6KB is sorted into the following speed grades: -11, -12, 12I, 12A, 12K -15, 15I,
15A and 15K. The -11 speed grade is compliant to the DDR3-1866 (13-13-13) specification. The -12,
12I, 12A and 12K speed grades are compliant to the DDR3-1600 (11-11-11) specification (the 12I
industrial grade which is guaranteed to support -40°C ≤ TCASE 95°C). The -15, 15I, 15A and 15K
speed grades are compliant to the DDR3-1333 (9-9-9) specification (the 15I industrial grade which is
guaranteed to support -40°C ≤ TCASE 95°C).
The automotive grade parts temperature, if offered, has two simultaneous requirements: ambient
temperature (TA) surrounding the device cannot be less than -40°C or greater than +95°C (for 12A
and 15A), +105°C (for 12K and 15K), and the case temperature (TCASE) cannot be less than -40°C or
greater than +95°C (for 12A and 15A), +105°C (for 12K and 15K). JEDEC specifications require the
refresh rate to double when TCASE exceeds +85°C; this also requires use of the high-temperature self
refresh option. Additionally, ODT resistance and the input/output impedance must be derated when
TCASE is < 0°C or > +85°C.
The W631GG6KB is designed to comply with the following key DDR3 SDRAM features such as
posted CAS#, programmable CAS# Write Latency (CWL), ZQ calibration, on die termination and
asynchronous reset. All of the control and address inputs are synchronized with a pair of externally
supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and
CK# falling). All I/Os are synchronized with a differential DQS-DQS# pair in a source synchronous
fashion.
2. FEATURES
Power Supply: VDD, VDDQ = 1.5V ± 0.075V
Double Data Rate architecture: two data transfers per clock cycle
Eight internal banks for concurrent operation
8 bit prefetch architecture
CAS Latency: 6, 7, 8, 9, 10, 11 and 13
Burst length 8 (BL8) and burst chop 4 (BC4) modes: fixed via mode register (MRS) or selectable On-
The-Fly (OTF)
Programmable read burst ordering: interleaved or nibble sequential
Bi-directional, differential data strobes (DQS and DQS#) are transmitted / received with data
Edge-aligned with read data and center-aligned with write data
DLL aligns DQ and DQS transitions with clock
Differential clock inputs (CK and CK#)
Commands entered on each positive CK edge, data and data mask are referenced to both edges of
a differential data strobe pair (double data rate)
Posted CAS with programmable additive latency (AL = 0, CL - 1 and CL - 2) for improved command,
address and data bus efficiency
Read Latency = Additive Latency plus CAS Latency (RL = AL + CL)
Auto-precharge operation for read and write bursts
Refresh, Self-Refresh, Auto Self-refresh (ASR) and Partial array self refresh (PASR)
Precharged Power Down and Active Power Down
Publication Release Date: Feb. 27, 2013
Revision A04
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W631GG6KB arduino
W631GG6KB
7. FUNCTIONAL DESCRIPTION
7.1 Basic Functionality
The DDR3 SDRAM is a high-speed dynamic random-access memory internally configured as an
eight-bank DRAM. The DDR3 SDRAM uses an 8n prefetch architecture to achieve high-speed
operation. The 8n prefetch architecture is combined with an interface designed to transfer two data
words per clock cycle at the I/O pins. A single read or write operation for the DDR3 SDRAM consists
of a single 8n-bit wide, four clock data transfer at the internal DRAM core and eight corresponding n-
bit wide, one-half clock cycle data transfers at the I/O pins.
Read and write operation to the DDR3 SDRAM are burst oriented, start at a selected location, and
continue for a burst length of eight or a ‗chopped‘ burst of four in a programmed sequence. Operation
begins with the registration of an Active command, which is then followed by a Read or Write
command. The address bits registered coincident with the Active command are used to select the
bank and row to be activated (BA0-BA2 select the bank; A0-A12 select the row). The address bits
registered coincident with the Read or Write command are used to select the starting column location
for the burst operation, determine if the auto precharge command is to be issued (via A10), and select
BC4 or BL8 mode ‗on the fly‘ (via A12) if enabled in the mode register.
Prior to normal operation, the DDR3 SDRAM must be powered up and initialized in a predefined
manner. The following sections provide detailed information covering device reset and initialization,
register definition, command descriptions, and device operation.
7.2 RESET and Initialization Procedure
7.2.1 Power-up Initialization Sequence
The following sequence is required for POWER UP and Initialization.
1. Apply power (RESET# is recommended to be maintained below 0.2 * VDD; all other inputs may be
undefined). RESET# needs to be maintained for minimum 200 µS with stable power. CKE is pulled
―Low‖ anytime before RESET# being de-asserted (min. time 10 nS). The power voltage ramp time
between 300 mV to VDD min. must be no greater than 200 mS; and during the ramp, VDD VDDQ
and (VDD - VDDQ) < 0.3 Volts.
VDD and VDDQ are driven from a single power converter output, AND
The voltage levels on all pins other than VDD, VDDQ, VSS, VSSQ must be less than or equal to
VDDQ and VDD on one side and must be larger than or equal to VSSQ and VSS on the other side.
In addition, VTT is limited to 0.95 V max once power ramp is finished, AND
VREF tracks VDDQ/2.
OR
Apply VDD without any slope reversal before or at the same time as VDDQ.
Apply VDDQ without any slope reversal before or at the same time as VTT & VREF.
The voltage levels on all pins other than VDD, VDDQ, VSS, VSSQ must be less than or equal to
VDDQ and VDD on one side and must be larger than or equal to VSSQ and VSS on the other side.
2. After RESET# is de-asserted, wait for another 500 µS until CKE becomes active. During this time,
the DRAM will start internal state initialization; this will be done independently of external clocks.
3. Clocks (CK, CK#) need to be started and stabilized for at least 10 nS or 5 tCK (which is larger)
before CKE goes active. Since CKE is a synchronous signal, the corresponding set up time to
clock (tIS) must be met. Also, a NOP or Deselect command must be registered (with tIS set up time
to clock) before CKE goes active. Once the CKE is registered ―High‖ after Reset, CKE needs to be
continuously registered ―High‖ until the initialization sequence is finished, including expiration of
tDLLK and tZQinit.
4. The DDR3 SDRAM keeps its on-die termination in high-impedance state as long as RESET# is
asserted. Further, the SDRAM keeps its on-die termination in high impedance state after RESET#
- 11 -
Publication Release Date: Feb. 27, 2013
Revision A04

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