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PDF IR3831MPbF Data sheet ( Hoja de datos )
| Número de pieza | IR3831MPbF | |
| Descripción | SYNCHRONOUS BUCK REGULATOR | |
| Fabricantes | International Rectifier | |
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PD60363
IR3831MPbF
SupIRBuckTM
HIGHLY EFFICIENT INTEGRATED
SYNCHRONOUS BUCK REGULATOR FOR DDR APPLICATIONS
Features
Description
• Wide Input Voltage Range 1.0V to 16V
The IR3831 SupIRBuckTM is an easy-to-use, fully
• Wide Output Voltage Range 0.6V to 0.9*Vin
integrated and highly efficient DC/DC regulator.
• Continuous 8A Load Capability
The MOSFETS co-packaged with the on-chip
• Integrated Bootstrap-diode
PWM controller make IR3831 a space-efficient
•
•
High Bandwidth E/A for excellent transient
performance
Programmable Switching Frequency up to 1.5 MHz
solution, providing accurate
DDR memory applications.
power
delivery
for
• Programmable Over Current Protection (Hiccup) IR3831 is configured to generate termination
• PGood output
voltage (VTT) for DDR memory applications.
• Programmable Soft-Start
• Enable Input with Voltage Monitoring Capability
• Enhanced Pre-Bias Start-up
• Vp input for DDR Tracking applications
• -40oC to 125oC operating junction temperature
• Thermal Protection
IR3831 offers programmability of start up time,
switching frequency and current limit while
operating in wide input and output voltage range.
The switching frequency is programmable from
250kHz to 1.5MHz for an optimum solution.
• 5mm x 6mm Power QFN Package, 0.9 mm height It also features important protection functions,
• Lead-free, halogen-free and RoHS compliant
such as Pre-Bias startup, hiccup current limit and
Applications
• Server Applications
thermal shutdown to give required system level
security in the event of fault conditions.
• Storage Applications
• Embedded Telecom Systems
• Distributed Point of Load Power Architectures
• Netcom Applications
1.0V <Vin<16V
4.5V <Vcc<5.5V
VDDQ
PGood
Enable
Vcc
PGood
Vp
Rt
SS/ SD Gnd
Vin Boot
SW
OCSet
Fb
Comp
PGnd
Vo
11/05/10
Fig. 1. Typical application diagram
1
1 page  
Recommended Operating Conditions
IR3831MPbF
Symbol
Vin
Vcc
Boot to SW
Vo
Io
Fs
Tj
Definition
Input Voltage
Supply Voltage
Supply Voltage
Output Voltage
Output Current
Switching Frequency
Junction Temperature
Min
Max
Units
1.0 16
4.5 5.5
4.5 5.5 V
0.6 0.90*Vin
0 8A
225
1650
kHz
-40 125 oC
Electrical Specifications
Unless otherwise specified, these specification apply over 4.5V< Vcc<5.5V, Vp=0.6V, Vin=12V,
0oC<Tj< 125oC. Typical values are specified at Ta = 25oC.
Parameter
Symbol
Power Loss
Power Loss
Ploss
MOSFET Rds(on)
Top Switch
Bottom Switch
Rds(on)_Top
Rds(on)_Bot
Supply Current
VCC Supply Current (Standby)
Vcc Supply Current (Dyn)
ICC(Standby)
ICC(Dyn)
Under Voltage Lockout
VCC-Start-Threshold
VCC-Stop-Threshold
VCC-Hysteresis
Enable-Start-Threshold
VCC_UVLO_Start
VCC_UVLO_Stop
Vcc-Hys
Enable_UVLO_Start
Enable-Stop-Threshold
Enable_UVLO_Stop
Enable-Hysteresis
Enable_Hys
Enable leakage current
Ien
Test Condition
Vcc=5V, Vin=12V, Vo=0.75V, Io=8A,
Fs=400kHz, L=0.6uH, Note4
VBoot -Vsw =5V, ID=10A, Tj=25oC
Vcc=5V, ID=10A, Tj=25oC
SS=0V, No Switching, Enable low
SS=3V, Vcc=5V, Fs=500kHz
Enable high
Vcc Rising Trip Level
Vcc Falling Trip Level
Supply ramping up and down
Supply ramping up
Supply ramping down
Supply ramping up and down
Enable=3.3V
Min
TYP MAX
Units
1.28
W
16.7
8.7
23
12
mΩ
500
12
μA
mA
4.06
3.76
0.25
1.14
0.9
0.16
4.26
4.46
3.96
4.16
0.3 0.38
1.2 1.36
1.0 1.06
0.2 0.24
18
V
μA
11/05/10
5
5 Page 
Circuit Description
THEORY OF OPERATION
Introduction
The IR3831 uses a PWM voltage mode control
scheme with external compensation to provide
good noise immunity and maximum flexibility in
selecting inductor values and capacitor types.
The switching frequency is programmable from
250kHz to 1.5MHz and provides the capability of
optimizing the design in terms of size and
performance.
IR3831 provides precisely regulated output
voltage programmed via two external resistors
from 0.7V to 0.9*Vin.
The IR3831 operates with an external bias
supply from 4.5V to 5.5V, allowing an extended
operating input voltage range from 1.0V to 16V.
The device utilizes the on-resistance of the low
side MOSFET as current sense element, this
method enhances the converter’s efficiency and
reduces cost by eliminating the need for external
current sense resistor.
IR3831 includes two low Rds(on) MOSFETs using
IR’s HEXFET technology. These are specifically
designed for high efficiency applications.
Under-Voltage Lockout and POR
The under-voltage lockout circuit monitors the
input supply Vcc and the Enable input. It assures
that the MOSFET driver outputs remain in the off
state whenever either of these two signals drop
below the set thresholds. Normal operation
resumes once Vcc and Enable rise above their
thresholds.
The POR (Power On Ready) signal is generated
when all these signals reach the valid logic level
(see system block diagram). When the POR is
asserted the soft start sequence starts (see soft
start section).
Enable
The Enable features another level of flexibility for
start up. The Enable has precise threshold which
is internally monitored by Under-Voltage Lockout
(UVLO) circuit. Therefore, the IR3831 will turn on
only when the voltage at the Enable pin exceeds
this threshold, typically, 1.2V.
11/05/10
IR3831MPbF
If the input to the Enable pin is derived from the
bus voltage by a suitably programmed resistive
divider, it can be ensured that the IR3831 does
not turn on until the bus voltage reaches the
desired level. Only after the bus voltage reaches
or exceeds this level will the voltage at Enable
pin exceed its threshold, thus enabling the
IR3831. Therefore, in addition to being a logic
input pin to enable the IR3831, the Enable
feature, with its precise threshold, also allows the
user to implement an Under-Voltage Lockout for
the bus voltage Vin. This is desirable particularly
for high output voltage applications, where we
might want the IR3831 to be disabled at least
until Vin exceeds the desired output voltage level.
Fig. 3a. Normal Start up, Device turns on
when the Bus voltage reaches 10.2V
Figure 3b. shows the recommended start-up
sequence for the non-tracking operation of
IR3831, when Enable is used as a logic input.
Fig. 3b. Recommended startup sequence,
Non-Tracking operation
11
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