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PDF PI4ULS3V204 Data sheet ( Hoja de datos )

Número de pieza PI4ULS3V204
Descripción 4-Bit Bi-directional Level Shifter
Fabricantes Pericom Semiconductor 
Logotipo Pericom Semiconductor Logotipo



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No Preview Available ! PI4ULS3V204 Hoja de datos, Descripción, Manual

PI4ULS3V204
4-Bit Bi-directional Level Shifter
for Open-drain and Push-pull Application
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Features
VCCA can be Less than, Greater than or Equal to
VCCB
1.1V to 3.6V on A Port and 1.1V to 3.6V on B
Port
High-Speed with 24 Mb/s Data Rate for push-pull
application
High-Speed with 2 Mb/s Data Rate for open-drain
application
No Direction-Control Signal Needed
Low Bit-to-Bit Skew
Non-preferential Power-up Sequencing
ESD protection exceeds 8000V HBM per
JESD22-A114
Integrated 10 kΩ Pull-up Resistors
Package: TSSOP-14,TQFN3.5x3.5-14,CSP-12
Description
The PI4ULS3V204 is a 4-bit configurable dual
supply bidirectional auto sensing translator that does
not require a directional control pin. The A and B ports
are designed to track two different power supply rails,
VCCA and VCCB respectively. Both the VCCA and VCCB
supply rails are configurable from 1.1V to 3.6V. This
allows voltage logic signals on the VCCA side to be
translated into lower, higher or equal value voltage
logic signals on the VCCB side, and vice-versa.
The translator has integrated 10 kΩ pull-up
resistors on the I/O lines. The integrated pull-up
resistors are used to pull-up the I/O lines to either VCCA
or VCCB. The PI4ULS3V204 is an excellent match for
open-drain applications such as the I2C communication
bus.
Applications
I2C, SMBus, MDIO
Low Voltage ASIC Level Translation
Mobile Phones, PDAs, Camera
Pin Configuration
.
TQFN3.5x3.5-14(Top View)
TSSOP-14(Top View)
2015-07-0031
CSP-12(Bottom View)
1
PT0511-2 08/18/15

1 page




PI4ULS3V204 pdf
PI4ULS3V204
4-Bit Bi-directional Level Shifter
for Open-drain and Push-pull Application
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Continuously.
Symbol
Parameter
VCCA= 1.8V±0.15V , VCCB = 1.2V±0.1V
tRB B port Rise Time
tFB B port Fall Time
tRA A port Rise Time
tFA A port Fall Time
tEN Enable Time
tDIS
tPHLAB
tPLHAB
tPHLBA
tPLHBA
tPPSKEW
MDR
Disable Time
Propagation Delay
(Driving A)
Propagation Delay
(Driving B)
Part-to-Part Skew
Maximum Data Rate
VCCA= 1.8V±0.15V, VCCB = 2.5V±0.2V
tRB B port Rise Time
tFB B port Fall Time
tRA A port Rise Time
tFA A port Fall Time
tEN Enable Time
tDIS
tPHL−A−B
tPLH−A−B
Disable Time
Propagation Delay
(Driving A)
tPHL−B−A
tPLH−B−A
Propagation Delay
(Driving B)
tPPSKEW
ParttoPart Skew
MDR
Maximum Data Rate
VCCA= 1.8V±0.15V, VCCB = 3.3V±0.3V
tRB B port Rise Time
tFB B port Fall Time
tRA A port Rise Time
tFA A port Fall Time
tEN Enable Time
tDIS
tPHL−A−B
tPLH−A−B
Disable Time
Propagation Delay
(Driving A)
tPHL−B−A
tPLH−B−A
Propagation Delay
(Driving B)
tPPSKEW
ParttoPart Skew
MDR
Maximum Data Rate
To be continued.
Test Conditions
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Min Typ
Max
25
25
14
25
200
200
10
15
12
12
1
20
8
8
6
12
200
150
5
4
4
4
1
24
8
8
4
10
180
120
6
4
4
4
1
24
Unit
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
Mbps
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
Mbps
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
Mbps
2015-07-0031
PT0511-2 08/18/15
5

5 Page





PI4ULS3V204 arduino
PI4ULS3V204
4-Bit Bi-directional Level Shifter
for Open-drain and Push-pull Application
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Input Driver Requirements
The rise (tR) and fall (tF) timing parameters of the open drain outputs depend on the magnitude of the pull−up
resistors. In -addition, the propagation times (tPD), skew (tPSKEW) and maximum data rate depend on the impedance of
the device that is connected to the translator. The timing parameters listed in the data sheet assume that the output
impedance of the drivers connected to the translator is less than 50 kΩ.
Enable Input (EN)
The PI4ULS3V204 has an Enable pin (EN) that provides tri-state operation at the I/O pins. Driving the Enable
pin to a low logic level minimizes the power consumption of the device and drives the I/O VCCB and I/O VCCA pins to a
high impedance state. Normal translation operation occurs when the EN pin is equal to a logic high signal. The EN
pin is referenced to the VCCA supply and has overvoltage tolerant protection.
Power Supply Guidelines
During normal operation, supply voltage VCCA can be greater than, less than or equal to VCCB. The sequencing of
the power supplies will not damage the device during the power up operation. For optimal performance, 0.01μF to
0.1μF decoupling capacitors should be used on the VCCA and VCCB power supply pins. Ceramic capacitors are a good
design choice to filter and bypass any noise signals on the voltage lines to the ground plane of the PCB. The
noise immunity will be maximized by placing the capacitors as close as possible to the supply and ground pins,
along with minimizing the PCB connection traces.
2015-07-0031
PT0511-2 08/18/15
11

11 Page







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