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PDF 28F400B3 Data sheet ( Hoja de datos )

Número de pieza 28F400B3
Descripción 3 Volt Advanced Boot Block Flash Memory
Fabricantes Intel 
Logotipo Intel Logotipo



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No Preview Available ! 28F400B3 Hoja de datos, Descripción, Manual

3 Volt Advanced Boot Block Flash
Memory
28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Preliminary Datasheet
Product Features
s Flexible SmartVoltage Technology
— 2.7 V–3.6 V Read/Program/Erase
— 12 V VPP Fast Production Programming
s 2.7 V or 1.65 V I/O Option
— Reduces Overall System Power
s High Performance
— 2.7 V–3.6 V: 70 ns Max Access Time
s Optimized Block Sizes
— Eight 8-KB Blocks for Data,Top or
Bottom Locations
— Up to One Hundred Twenty-Seven 64-
KB Blocks for Code
s Block Locking
— VCC-Level Control through WP#
s Low Power Consumption
— 9 mA Typical Read Current
s Absolute Hardware-Protection
— VPP = GND Option
— VCC Lockout Voltage
s Extended Temperature Operation
— –40 °C to +85 °C
s Automated Program and Block Erase
— Status Registers
s Intel® Flash Data Integrator Software
— Flash Memory Manager
— System Interrupt Manager
— Supports Parameter Storage, Streaming
Data (e.g., Voice)
s Extended Cycling Capability
— Minimum 100,000 Block Erase Cycles
Guaranteed
s Automatic Power Savings Feature
— Typical ICCS after Bus Inactivity
s Standard Surface Mount Packaging
— 48-Ball CSP Packages
— 40- and 48-Lead TSOP Packages
s Density and Footprint Upgradeable for
common package
— 4-, 8-, 16-, 32- and 64-Mbit Densities
s ETOX™ VII (0.18 µ) Flash Technology
— 28F160/320/640B3xC
— 4-, 8-, 16-, and 32-Mbit also exist on
ETOX™ V (0.4µ) and/or ETOX ™ VI
(0.25µ) Flash Technology
s x8 not recommended for new designs
s 4-Mbit density not recommended for new
designs
The 3 Volt Advanced Boot Block flash memory, manufactured on Intel’s latest 0.18 µm
technology, represents a feature-rich solution at overall lower system cost. The 3 Volt Advanced
Boot Block flash memory products in x16 will be available in 48-lead TSOP and 48-ball CSP
packages. The x8 option of this product family will only be available in 40-lead TSOP and 48-
ball µBGA* packages. Additional information on this product family can be obtained by
accessing Intel’s website at: http://www.intel.com/design/flash.
Notice: This document contains preliminary information on new products in production. The
specifications are subject to change without notice. Verify with your local Intel sales office that
you have the latest datasheet before finalizing a design.
Order Number: 290580-012
October 2000

1 page




28F400B3 pdf
28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Revision History
Number
-001
-002
-003
-004
-005
-006
-007
Description
Original version
Section 3.4, VPP Program and Erase Voltages, added
Updated Figure 9: Automated Block Erase Flowchart
Updated Figure 10: Erase Suspend/Resume Flowchart (added program to table)
Updated Figure 16: AC Waveform: Program and Erase Operations (updated notes)
IPPR maximum specification change from ±25 µA to ±50 µA
Program and Erase Suspend Latency specification change
Updated Appendix A: Ordering Information (included 8 M and 4 M information)
Updated Figure, Appendix D: Architecture Block Diagram (Block info. in words not bytes)
Minor wording changes
Combined byte-wide specification (previously 290605) with this document
Improved speed specification to 80 ns (3.0 V) and 90 ns (2.7 V)
Improved 1.8 V I/O option to minimum 1.65 V (Section 3.4)
Improved several DC characteristics (Section 4.4)
Improved several AC characteristics (Sections 4.5 and 4.6)
Combined 2.7 V and 1.8 V DC characteristics (Section 4.4)
Added 5 V VPP read specification (Section 3.4)
Removed 120 ns and 150 ns speed offerings
Moved Ordering Information from Appendix to Section 6.0; updated information
Moved Additional Information from Appendix to Section 7.0
Updated figure Appendix B, Access Time vs. Capacitive Load
Updated figure Appendix C, Architecture Block Diagram
Moved Program and Erase Flowcharts to Appendix E
Updated Program Flowchart
Updated Program Suspend/Resume Flowchart
Minor text edits throughout
Added 32-Mbit density
Added 98H as a reserved command (Table 4)
A1–A20 = 0 when in read identifier mode (Section 3.2.2)
Status register clarification for SR3 (Table 7)
VCC and VCCQ absolute maximum specification = 3.7 V (Section 4.1)
Combined IPPW and ICCW into one specification (Section 4.4)
Combined IPPE and ICCE into one specification (Section 4.4)
Max Parameter Block Erase Time (tWHQV2/tEHQV2) reduced to 4 sec (Section 4.7)
Max Main Block Erase Time (tWHQV3/tEHQV3) reduced to 5 sec (Section 4.7)
Erase suspend time @ 12 V (tWHRH2/tEHRH2) changed to 5 µs typical and 20 µs maximum
(Section 4.7)
Ordering Information updated (Section 6.0)
Write State Machine Current/Next States Table updated (Appendix A)
Program Suspend/Resume Flowchart updated (Appendix F)
Erase Suspend/Resume Flowchart updated (Appendix F)
Text clarifications throughout
µBGA package diagrams corrected (Figures 3 and 4)
IPPD test conditions corrected (Section 4.4)
32-Mbit ordering information corrected (Section 6)
µBGA package top side mark information added (Section 6)
VIH and VILSpecification change (Section 4.4)
ICCS test conditions clarification (Section 4.4)
Added Command Sequence Error Note (Table 7)
Datasheet renamed from Smart 3 Advanced Boot Block 4-Mbit, 8-Mbit, 16-Mbit Flash
Memory Family.
Added device ID information for 4-Mbit x8 device
Removed 32-Mbit x8 to reflect product offerings
Minor text changes
Corrected RP# pin description in Table 2, 3 Volt Advanced Boot Block Pin Descriptions
Corrected typographical error fixed in Ordering Information
3UHOLPLQDU\
v

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28F400B3 arduino
28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Figure 4. x16 48-Ball Very Thin Profile Pitch BGA and µBGA* Chip Size Package (Top View,
Ball Down)
1234567
16M
A A13
A11
A8
VPP WP# A19
A7
8
A4
B A14
A10
WE#
RP#
A18
A17
A5
64M 32M
C A15
A12
A9
A21 A20
A6
A3
A2
A1
D A16
D14
D5
D11
D2
D8 CE# A0
E VCCQ
D15
D6
D12
D3
D9
D0 GND
F GND
D7
D13
D4
VCC
D10
D1 OE#
NOTES:
0580_03
1. Shaded connections indicate the upgrade address connections. Lower density devices will not have the
upper address solder balls. Routing is not recommended in this area. A19 is the upgrade address for the
16-Mbit device. A20 is the upgrade address for the 32-Mbit device. A21 is the upgrade address for the 64-Mbit
device.
2. 4-Mbit density not available in µBGA CSP.
Table 2, “3 Volt Advanced Boot Block Pin Descriptions” on page 6 details the usage of each device
pin.
3UHOLPLQDU\
5

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