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PDF 74HCT4020 Data sheet ( Hoja de datos )

Número de pieza 74HCT4020
Descripción 14-stage binary ripple counter
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No Preview Available ! 74HCT4020 Hoja de datos, Descripción, Manual

74HC4020; 74HCT4020
14-stage binary ripple counter
Rev. 6 — 3 February 2016
Product data sheet
1. General description
The 74HT4020; 74HCT4020 is a 14-stage binary ripple counter with a clock input (CP), an
overriding asynchronous master reset input (MR) and 12 buffered parallel outputs (Q0,
and Q3 to Q13). The counter advances on the HIGH-to-LOW transition of CP. A HIGH on
MR clears all counter stages and forces all outputs LOW, independent of the state of CP.
Each counter stage is a static toggle flip-flop. This device features reduced input threshold
levels to allow interfacing to TTL logic levels. Inputs also include clamp diodes, this
enables the use of current limiting resistors to interface inputs to voltages in excess of
VCC.
2. Features and benefits
Wide supply voltage range from 2.0 V to 6.0 V
Input levels:
For 74HC4020: CMOS level
For 74HCT4020: TTL level
Multiple package options
Complies with JEDEC standard no. 7A
Specified from 40 C to +85 C and from 40 C to +125 C
3. Applications
Frequency dividing circuits
Time delay circuits
Control counters
4. Ordering information
Table 1. Ordering information
Type number Package
Temperature range
74HC4020D 40 C to +125 C
74HCT4020D
74HC4020DB 40 C to +125 C
74HCT4020DB
Name
SO16
SSOP16
Description
plastic small outline package; 16 leads;
body width 3.9 mm
Version
SOT109-1
plastic shrink small outline package; 16 leads; body SOT338-1
width 5.3 mm

1 page




74HCT4020 pdf
NXP Semiconductors
74HC4020; 74HCT4020
14-stage binary ripple counter
8. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min Max Unit
VCC
IIK
IOK
IO
ICC
IGND
Tstg
Ptot
supply voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
VI < 0.5 V or VI > VCC + 0.5 V
VI < 0.5 V or VI > VCC + 0.5 V
0.5 V < VO < VCC + 0.5 V
Tamb = 40 C to +125 C
SO16, SSOP16, TSSOP16 and
DHVQFN16 packages
0.5
-
-
-
-
-
65
[1]
-
+7
20
20
25
50
50
+150
V
mA
mA
mA
mA
mA
C
500 mW
[1] For SO16 package: Ptot derates linearly with 8 mW/K above 70 C.
For SSOP16 and TSSOP16 packages: Ptot derates linearly with 5.5 mW/K above 60 C.
For DHVQFN16 package: Ptot derates linearly with 4.5 mW/K above 60 C.
9. Recommended operating conditions
Table 5. Recommended operating conditions
Symbol Parameter
Conditions
VCC
VI
VO
t/V
Tamb
supply voltage
input voltage
output voltage
input transition rise and
fall rate
ambient temperature
except for
Schmitt trigger inputs
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
74HC4020
Min Typ Max
2.0 5.0 6.0
0 - VCC
0 - VCC
74HCT4020
Min Typ Max
4.5 5.0 5.5
0 - VCC
0 - VCC
Unit
V
V
V
- - 625 - - - ns/V
- 1.67 139 - 1.67 139 ns/V
- - 83 - - - ns/V
40 +25 +125 40 +25 +125 C
74HC_HCT4020
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 3 February 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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74HCT4020 arduino
NXP Semiconductors
74HC4020; 74HCT4020
14-stage binary ripple counter
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Test data is given in Table 9.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
Fig 10. Test circuit for measuring switching times
Table 9. Test data
Type
Input
74HC4020
74HCT4020
VI
VCC
3V
tr, tf
6 ns
6 ns
Load
CL
15 pF, 50 pF
15 pF, 50 pF
74HC_HCT4020
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 3 February 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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