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PDF VS1103b Data sheet ( Hoja de datos )
| Número de pieza | VS1103b | |
| Descripción | MIDI/ADPCM AUDIO CODEC | |
| Fabricantes | VLSI | |
| Logotipo |  |
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VS1103b Datasheet
VS1103b - MIDI/ADPCM AUDIO
CODEC
Features
Description
• Mixes three audio sources
– General MIDI 1+ / SP-MIDI
– WAV (PCM + IMA ADPCM)
– Microphone or line input
• Encodes IMA ADPCM from microphone,
line input or mixed output
• Input streams can use different sample
rates
• EarSpeaker Spatial Processing
• Bass and treble controls
• Operates with a single 12. . . 13 MHz clock
• Internal PLL clock multiplier
• Low-power operation
• High-quality on-chip stereo DAC with no
phase error between channels
• Stereo earphone driver capable of driv-
ing a 30Ω load
• Separate operating voltages for analog,
digital and I/O
• 5.5 KiB On-chip RAM for user code /
data
• Serial control and data interfaces
• Can be used as a slave co-processor
• SPI flash boot for special applications
• UART for debugging purposes
• New functions may be added with soft-
ware and 4 GPIO pins
VS1103b is a single-chip MIDI/ADPCM/WAV
audio decoder and ADPCM encoder that can
handle upto three simultaneous audio streams.
It can also act as a Midi synthesizer.
VS1103b contains a high-performance, pro-
prietary low-power DSP processor core VS_DSP4,
working data memory, 5 KiB instruction RAM
and 0.5 KiB data RAM for user applications,
serial control and input data interfaces, 4 gen-
eral purpose I/O pins, an UART, as well as a
high-quality variable-sample-rate mono ADC
and stereo DAC, followed by an earphone am-
plifier and a common buffer.
VS1103b receives its input bitstreams through
serial input buses, which it listens to as a sys-
tem slave. The input streams are decoded
and passed through digital volume controls to
an 18-bit oversampling, multi-bit, sigma-delta
DAC. Decoding is controlled via a serial con-
trol bus. In addition to basic decoding, it is
possible to add application specific features,
like DSP effects, to user RAM memory.
mic
audio
line
audio
GPIO
VS1103
MIC AMP
MUX
4
GPIO
DREQ
SO
SI
SCLK
XCS
XDCS
Serial
Data/
Control
Interface
RX
TX UART
Mono
ADC
Stereo
DAC
VSDSP4
Clock
multiplier
Instruction
RAM
Instruction
ROM
Stereo Ear−
phone Driver
X ROM
audio
L
R
output
X RAM
Y ROM
Y RAM
Version: 1.03, 2014-12-19
1
1 page  
VS1103b Datasheet
CONTENTS
8.1 Who Needs to Read This Chapter . . . . . . . . . . . . . . . . . . . . . . . . . . 45
8.2 The Processor Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
8.3 VS1103b Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
8.4 SCI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
8.5 Serial Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
8.6 DAC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
8.7 GPIO Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
8.8 Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
8.9 A/D Modulator Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
8.10 Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
8.10.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
8.11 UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
8.11.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
8.11.2 Status UARTx_STATUS . . . . . . . . . . . . . . . . . . . . . . . . . 51
8.11.3 Data UARTx_DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
8.11.4 Data High UARTx_DATAH . . . . . . . . . . . . . . . . . . . . . . . . 52
8.11.5 Divider UARTx_DIV . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
8.11.6 Interrupts and Operation . . . . . . . . . . . . . . . . . . . . . . . . . 52
8.12 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
8.12.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
8.12.2 Configuration TIMER_CONFIG . . . . . . . . . . . . . . . . . . . . . 54
8.12.3 Configuration TIMER_ENABLE . . . . . . . . . . . . . . . . . . . . . 54
8.12.4 Timer X Startvalue TIMER_Tx[L/H] . . . . . . . . . . . . . . . . . . . 55
8.12.5 Timer X Counter TIMER_TxCNT[L/H] . . . . . . . . . . . . . . . . . . 55
8.12.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
8.13 System Vector Tags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
8.13.1 AudioInt, 0x20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
8.13.2 SciInt, 0x21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
8.13.3 DataInt, 0x22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
8.13.4 ModuInt, 0x23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Version: 1.03, 2014-12-19
5
5 Page 
VS1103b Datasheet
3 CHARACTERISTICS & SPECIFICATIONS
3.4 Power Consumption
TBD
3.5 Digital Characteristics
Parameter
Symbol Min Typ Max Unit
High-Level Input Voltage
0.7×IOVDD
IOVDD+0.31 V
Low-Level Input Voltage
-0.2 0.3×IOVDD V
High-Level Output Voltage at IO = -1.0 mA
Low-Level Output Voltage at IO = 1.0 mA
Input Leakage Current
SPI Input Clock Frequency 2
Rise time of all output pins, load = 50 pF
0.7×IOVDD
-1.0
0.3×IOVDD
1.0
C LK I
7
50
V
V
µA
MHz
ns
1 Must not exceed 3.6V
2
Value
for
SCI
reads.
SCI
and
SDI
writes
allow
C
LK
4
I
.
3.6 Switching Characteristics - Boot Initialization
Parameter
Symbol Min Max Unit
XRESET active time
XRESET inactive to software ready
2 XTALI
16600 500001 XTALI
Power on reset, rise time to CVDD 10 V/s
1 DREQ rises when initialization is complete. You should not send any data or commands
before that.
Version: 1.03, 2014-12-19
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet VS1103b.PDF ] | |
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