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PDF VS1003 Data sheet ( Hoja de datos )
| Número de pieza | VS1003 | |
| Descripción | MP3/WMA AUDIO CODEC | |
| Fabricantes | VLSI | |
| Logotipo |  |
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1. VS1003 datasheet pinout  Hay una vista previa y un enlace de descarga de VS1003 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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VS1003
VS1003 - MP3/WMA AUDIO CODEC
Features
• Decodes MPEG 1 & 2 audio layer III
(CBR +VBR +ABR); WMA 4.0/4.1/7/8/9
all profiles (5-384kbit/s); WAV (PCM +
IMA ADPCM); General MIDI / SP-MIDI
files
• Encodes IMA ADPCM from microphone
or line input
• Streaming support for MP3 and WAV
• Bass and treble controls
• Operates with a single 12..13 MHz clock
• Internal PLL clock multiplier
• Low-power operation
• High-quality on-chip stereo DAC with no
phase error between channels
• Stereo earphone driver capable of driv-
ing a 30Ω load
• Separate operating voltages for analog,
digital and I/O
• 5.5 KiB On-chip RAM for user code /
data
• Serial control and data interfaces
• Can be used as a slave co-processor
• SPI flash boot for special applications
• UART for debugging purposes
• New functions may be added with soft-
ware and 4 GPIO pins
Description
VS1003 is a single-chip MP3/WMA/MIDI au-
dio decoder and ADPCM encoder. It contains
a high-performance, proprietary low-power DSP
processor core VS_DSP4, working data mem-
ory, 5 KiB instruction RAM and 0.5 KiB data
RAM for user applications, serial control and
input data interfaces, 4 general purpose I/O
pins, an UART, as well as a high-quality variable-
sample-rate mono ADC and stereo DAC, fol-
lowed by an earphone amplifier and a com-
mon buffer.
VS1003 receives its input bitstream through
a serial input bus, which it listens to as a
system slave. The input stream is decoded
and passed through a digital volume control
to an 18-bit oversampling, multi-bit, sigma-
delta DAC. The decoding is controlled via a
serial control bus. In addition to the basic de-
coding, it is possible to add application spe-
cific features, like DSP effects, to the user
RAM memory.
mic
audio
line
audio
GPIO
VS1003
MIC AMP
MUX
4
GPIO
DREQ
SO
SI
SCLK
XCS
XDCS
Serial
Data/
Control
Interface
RX
TX UART
Mono
ADC
Stereo
DAC
VSDSP4
Clock
multiplier
Instruction
RAM
Instruction
ROM
Stereo Ear−
phone Driver
X ROM
audio
L
R
output
X RAM
Y ROM
Y RAM
Version: 1.08, 2014-12-19
1
1 page  
VS1003
LIST OF FIGURES
List of Figures
1 Measured ADC performance of the LINEIN pin. . . . . . . . . . . . . . . . . . . . 10
2 Measured ADC performance of the MIC pins (differential). . . . . . . . . . . . . . 10
3 Measured performance of RIGHT (or LEFT) output. . . . . . . . . . . . . . . . . 11
4 Typical spectrum of RIGHT (or LEFT) output. . . . . . . . . . . . . . . . . . . . . 11
5 Pin Configuration, LQFP-48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
6 Pin Configuration, BGA-49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
7 Typical Connection Diagram Using LQFP-48. . . . . . . . . . . . . . . . . . . . . 15
8 BSYNC Signal - one byte transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . 18
9 BSYNC Signal - two byte transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . 18
10 SCI Word Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
11 SCI Word Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
12 SPI Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
13 Two SCI Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
14 Two SDI Bytes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
15 Two SDI Bytes Separated By an SCI Operation. . . . . . . . . . . . . . . . . . . . 22
16 Data Flow of VS1003. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
17 ADPCM Frequency Responses with 8kHz sample rate. . . . . . . . . . . . . . . 30
18 User’s Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
19 RS232 Serial Interface Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Version: 1.08, 2014-12-19
5
5 Page 
VS1003
4 CHARACTERISTICS & SPECIFICATIONS
4.7.3 RIGHT and LEFT outputs
100
80
60
40
20
0
0.001
SNR 30R LOAD
SNR AWEIGHT 30R LOAD
THD 30R LOAD
THD NO LOAD
0.01 0.1
output voltage (rms)
1
Figure 3: Measured performance of RIGHT (or LEFT) output.
Measured performance of RIGHT (or LEFT) output with 1 kHz generated sine. Sampling rate
of DAC is 48 kHz (master clock 12.288 MHz), noise calculated from 0 to 20 kHz.
0
-20
-40
-60
-80
-100
-120
0
5000
10000
15000
frequency Hz
20000
Figure 4: Typical spectrum of RIGHT (or LEFT) output.
Typical spectrum of RIGHT (or LEFT) output with maximum level and 30 Ohm load. Setup is
the same is in Fig. 3.
Version: 1.08, 2014-12-19
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet VS1003.PDF ] | |
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