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PDF C8051F366 Data sheet ( Hoja de datos )

Número de pieza C8051F366
Descripción Mixed Signal ISP Flash MCU Family
Fabricantes Silicon Laboratories 
Logotipo Silicon Laboratories Logotipo



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C8051F360/1/2/3/4/5/6/7/8/9
Mixed Signal ISP Flash MCU Family
Analog Peripherals
- 10-Bit ADC (‘F360/1/2/6/7/8/9 only)
Up to 200 ksps
Up to 21 external single-ended or differential inputs
VREF from internal VREF, external pin or VDD
Internal or external start of conversion source
Built-in temperature sensor
- 10-Bit Current Output DAC
(‘F360/1/2/6/7/8/9 only)
- Two Comparators
Programmable hysteresis and response time
Configurable as interrupt or reset source
Low current (TBD µA)
- Brown-out detector and POR Circuitry
On-Chip Debug
- On-chip debug circuitry facilitates full speed, non-
intrusive in-system debug (no emulator required)
- Provides breakpoints, single stepping,
inspect/modify memory and registers
- Superior performance to emulation systems using
ICE-chips, target pods, and sockets
- Low cost, complete development kit
Supply Voltage
- Range: 2.7–3.6 V (50 MIPS) 3.0–3.6 V (100 MIPS)
(See Table 3.1)
- Power saving suspend and shutdown modes
High Speed 8051 µC Core
- Pipelined instruction architecture; executes 70% of
instructions in 1 or 2 system clocks
- 100 MIPS or 50 MIPS throughput with on-chip PLL
- Expanded interrupt handler
- 2-cycle 16 x 16 MAC engine
Memory
- 1280 bytes internal data RAM (256 + 1024)
- 32 kB (‘F360/1/2/3/4/5/6/7) or 16 kB (‘F368/9) Flash;
In-system programmable in 1024-byte Sectors—
1024 bytes are reserved in the 32 kB devices
Digital Peripherals
- up to 39 Port I/O; All 5 V tolerant with high sink cur-
rent
- Hardware enhanced UART, SMBus™, and
enhanced SPI™ serial ports
- Four general purpose 16-bit counter/timers
- 16-Bit programmable counter array (PCA) with six
capture/compare modules
- Real time clock mode using PCA or timer and exter-
nal clock source
- External Memory Interface (EMIF)
Clock Sources
- Two internal oscillators:
24.5 MHz with ±2% accuracy supports crystal-less
UART operation
80/40/20/10 kHz low frequency, low power
- Flexible PLL technology
- External oscillator: Crystal, RC, C, or clock
(1 or 2 pin modes)
- Can switch between clock sources on-the-fly; useful
in power saving modes
Packages
- 48-pin TQFP (C8051F360/3)
- 32-pin LQFP (C8051F361/4/6/8)
- 28-pin QFN (C8051F362/5/7/9)
Temperature Range: –40 to +85 °C (See
Table 3.1)
ANALOG
PERIPHERALS
VOLTAGE
+
+
COMPARATORS
-
-
A 10-bit
M
U
200 ksps
X ADC
‘F360/1/2/6/7/8/9 only
TEMP
SENSOR
10-bit
Current
DAC
DIGITAL I/O
UART
SMBus
Port 0
SPI
PCA
Port 1
Timer 0
Timer 1
Port 2
Timer 2
Timer 3
Port 3
Port 3
48-pin only
Port 4
HIGH-SPEED CONTROLLER CORE
WDT
16 x 16
MAC
8051 CPU
(100 or 50 MIPS)
1024 B
SRAM
POR
FLEXIBLE
DEBUG Internal Oscillator / 32/16 KB
INTERRUPTS CIRCUITRY
LFO / PLL
ISP FLASH
Rev. 0.2 1/07
Copyright © 2007 by Silicon Laboratories
C8051F36x
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.

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C8051F366 pdf
C8051F360/1/2/3/4/5/6/7/8/9
13.3.2.16.4.2 PSWE Maintenance .................................................................... 147
13.3.3.System Clock ......................................................................................... 147
13.4.Flash Read Timing ......................................................................................... 149
14. Branch Target Cache ........................................................................................... 151
14.1.Cache and Prefetch Operation ....................................................................... 151
14.2.Cache and Prefetch Optimization................................................................... 152
15. External Data Memory Interface and On-Chip XRAM........................................ 159
15.1.Accessing XRAM............................................................................................ 159
15.1.1.16-Bit MOVX Example ........................................................................... 159
15.1.2.8-Bit MOVX Example ............................................................................. 159
15.2.Configuring the External Memory Interface .................................................... 160
15.3.Port Configuration........................................................................................... 160
15.4.Multiplexed and Non-multiplexed Selection.................................................... 163
15.4.1.Multiplexed Configuration....................................................................... 163
15.4.2.Non-multiplexed Configuration............................................................... 164
15.5.Memory Mode Selection................................................................................. 165
15.5.1.Internal XRAM Only ............................................................................... 165
15.5.2.Split Mode without Bank Select.............................................................. 165
15.5.3.Split Mode with Bank Select................................................................... 166
15.5.4.External Only.......................................................................................... 166
15.6.Timing .......................................................................................................... 166
15.6.1.Non-multiplexed Mode ........................................................................... 168
15.6.2.Multiplexed Mode ................................................................................... 171
16. Oscillators ............................................................................................................. 175
16.1.Programmable Internal High-Frequency (H-F) Oscillator ............................... 175
16.1.1. Internal Oscillator Suspend Mode ......................................................... 176
16.2.Programmable Internal Low-Frequency (L-F) Oscillator ................................ 177
16.2.1.Calibrating the Internal L-F Oscillator..................................................... 178
16.3.External Oscillator Drive Circuit...................................................................... 178
16.4.System Clock Selection.................................................................................. 179
16.5.External Crystal Example ............................................................................... 181
16.6.External RC Example ..................................................................................... 182
16.7.External Capacitor Example ........................................................................... 182
16.8.Phase-Locked Loop (PLL).............................................................................. 183
16.8.1.PLL Input Clock and Pre-divider ............................................................ 183
16.8.2.PLL Multiplication and Output Clock ...................................................... 183
16.8.3.Powering on and Initializing the PLL ...................................................... 184
17. Port Input/Output.................................................................................................. 189
17.1.Priority Crossbar Decoder .............................................................................. 191
17.2.Port I/O Initialization ....................................................................................... 193
17.3.General Purpose Port I/O ............................................................................... 196
18. SMBus ................................................................................................................... 209
18.1.Supporting Documents ................................................................................... 210
18.2.SMBus Configuration...................................................................................... 210
Rev. 0.2
5

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C8051F366 arduino
C8051F360/1/2/3/4/5/6/7/8/9
18. SMBus
Figure 18.1. SMBus Block Diagram ...................................................................... 209
Figure 18.2. Typical SMBus Configuration ............................................................ 210
Figure 18.3. SMBus Transaction ........................................................................... 211
Figure 18.4. Typical SMBus SCL Generation ........................................................ 214
Figure 18.5. Typical Master Transmitter Sequence ............................................... 220
Figure 18.6. Typical Master Receiver Sequence ................................................... 221
Figure 18.7. Typical Slave Receiver Sequence ..................................................... 222
Figure 18.8. Typical Slave Transmitter Sequence ................................................. 223
19. UART0
Figure 19.1. UART0 Block Diagram ...................................................................... 227
Figure 19.2. UART0 Baud Rate Logic ................................................................... 228
Figure 19.3. UART Interconnect Diagram ............................................................. 229
Figure 19.4. 8-Bit UART Timing Diagram .............................................................. 229
Figure 19.5. 9-Bit UART Timing Diagram .............................................................. 230
Figure 19.6. UART Multi-Processor Mode Interconnect Diagram ......................... 231
20. Enhanced Serial Peripheral Interface (SPI0)
Figure 20.1. SPI Block Diagram ............................................................................ 237
Figure 20.2. Multiple-Master Mode Connection Diagram ...................................... 240
Figure 20.3. 3-Wire Single Master and 3-Wire Single Slave Mode
Connection Diagram ......................................................................... 240
Figure 20.4. 4-Wire Single Master Mode and 4-Wire Slave Mode
Connection Diagram ......................................................................... 240
Figure 20.5. Master Mode Data/Clock Timing ....................................................... 242
Figure 20.6. Slave Mode Data/Clock Timing (CKPHA = 0) ................................... 243
Figure 20.7. Slave Mode Data/Clock Timing (CKPHA = 1) ................................... 243
Figure 20.8. SPI Master Timing (CKPHA = 0) ....................................................... 247
Figure 20.9. SPI Master Timing (CKPHA = 1) ....................................................... 247
Figure 20.10. SPI Slave Timing (CKPHA = 0) ....................................................... 248
Figure 20.11. SPI Slave Timing (CKPHA = 1) ....................................................... 248
21. Timers
Figure 21.1. T0 Mode 0 Block Diagram ................................................................. 253
Figure 21.2. T0 Mode 2 Block Diagram ................................................................. 254
Figure 21.3. T0 Mode 3 Block Diagram ................................................................. 255
Figure 21.4. Timer 2 16-Bit Mode Block Diagram ................................................. 260
Figure 21.5. Timer 2 8-Bit Mode Block Diagram ................................................... 261
Figure 21.6. Timer 3 16-Bit Mode Block Diagram ................................................. 264
Figure 21.7. Timer 3 8-Bit Mode Block Diagram ................................................... 265
22. Programmable Counter Array
Figure 22.1. PCA Block Diagram ........................................................................... 269
Figure 22.2. PCA Counter/Timer Block Diagram ................................................... 270
Figure 22.3. PCA Interrupt Block Diagram ............................................................ 271
Figure 22.4. PCA Capture Mode Diagram ............................................................. 272
Figure 22.5. PCA Software Timer Mode Diagram ................................................. 273
Figure 22.6. PCA High Speed Output Mode Diagram ........................................... 274
Rev. 0.2
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