|
|
PDF WM8998 Data sheet ( Hoja de datos )
| Número de pieza | WM8998 | |
| Descripción | High Performance Audio Hub CODEC | |
| Fabricantes | Wolfson Microelectronics | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de WM8998 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
w
WM8998
High Performance Audio Hub CODEC
DESCRIPTION
The WM8998[1] is a highly-integrated low-power audio hub
CODEC for smartphones, tablets and other portable audio
devices. It is optimised for use in multimedia devices where
the audio processing requirements are implemented on the
host applications processor.
The WM8998 digital core combines fixed-function signal
processing blocks with a fully-flexible, all-digital audio mixing
and routing engine, for extensive use-case flexibility. Signal
processing blocks include filters, EQ, dynamics processors
and sample rate converters.
A SLIMbus interface supports multi-channel audio paths and
host control register access. Multiple sample rates are
supported concurrently via the SLIMbus interface. Three
further digital audio interfaces are provided, each supporting
a wide range of standard audio sample rates and serial
interface formats. Automatic sample rate detection enables
seamless wideband/narrowband voice call handover.
The stereo headphone driver provides ground-referenced
outputs, with noise levels as low as 1μVRMS for hi-fi quality
line or headphone output. The CODEC also features a
stereo line output, stereo 2W Class-D speaker outputs, a
dedicated BTL earpiece output, PDM for external speaker
amplifiers, and an IEC-60958-3 compatible S/PDIF
transmitter. A signal generator for controlling haptics devices
is included; vibe actuators can connect directly to the Class-
D speaker output, or via an external driver on the PDM
output interface. All inputs, outputs and system interfaces
can function concurrently.
The WM8998 supports up to six analogue mic/line inputs,
and up to three PDM digital inputs. The input multiplexers
support up to three signal paths. Microphone activity
detection with interrupt is available. A smart accessory
interface supports most standard 3.5mm accessories.
Impedance sensing and measurement is provided for
external accessory and push-button detection.
The WM8998 power, clocking and output driver
architectures are all designed to maximise battery life in
voice, music and standby modes. Low-power ‘Sleep’ is
supported, with configurable wake-up events. The WM8998
is powered from a 1.8V external supply. A separate supply
is required for the Class D speaker drivers (typically direct
connection to 4.2V battery).
Two integrated FLLs provide support for a wide range of
system clock frequencies. The WM8998 is configured using
the I2C or SLIMbus interfaces. The fully-differential internal
analogue architecture, minimal analogue signal paths and
on-chip RF noise filters ensure a very high degree of noise
immunity.
FEATURES
• Hi-Fi audio hub CODEC for mobile applications
• Digital audio processing core
- Fully flexible digital signal routing and mixing
- Wind noise, sidetone and other programmable filters
- Dynamic Range Control (compressor, limiter)
- Fully parametric EQs
- Low-pass / High-pass filters
• Multi-channel asynchronous sample rate conversion
• Integrated multi-channel 24-bit hi-fi audio hub CODEC
- 3 ADCs, 96dB SNR microphone input (48kHz)
- 7 DACs, 122dB SNR headphone playback (48kHz)
• Audio inputs
- Up to 6 analogue or 3 digital microphone inputs
- Single-ended or differential mic/line inputs
• Stereo headphone output driver
- 28mW into 32Ω load at 0.1% THD+N
- 6.9mW typical headphone playback power consumption
- Pop suppression functions
- 1µVRMS noise floor (A-weighted)
• Ground-referenced line output driver
- Stereo single-ended or Mono differential configuration
• Mono BTL earpiece output driver
- 100mW into 32Ω BTL load at 5% THD+N
• Stereo (2 x 2W) Class D speaker output drivers
- Direct drive of external haptics vibe actuators
• Two-channel digital speaker (PDM) output interface
• IEC-60958-3 compatible S/PDIF transmitter
• SLIMbus audio and control interface
• 3 full digital audio interfaces
- Standard sample rates from 8kHz up to 192kHz
- TDM support on all AIFs
- 6 channel input and output on AIF1 and AIF2
• Flexible clocking, derived from MCLKn, BCLKn or SLIMbus
• 2 low-power FLLs support reference clocks down to 32kHz
• Advanced accessory detection functions
- Low-power standby mode and configurable wake-up
• Configurable functions on 5 GPIO pins
• Integrated LDO regulators and charge pumps
• Support for single 1.8V supply operation
• Small W-CSP package, 0.4mm pitch
APPLICATIONS
• Smartphones and Multimedia handsets
• Tablets and Mobile Internet Devices (MID)
WOLFSON MICROELECTRONICS plc
Production Data, October 2014, Rev 4.0
[1] This product is protected by Patents US 7,622,984, US 7,626,445, US 7,765,019 and GB 2,432,765
Copyright 2014 Wolfson Microelectronics plc
1 page  
Production Data
WM8998
INTERRUPT CONTROL......................................................................................................................................................... 177
GENERAL PURPOSE INPUT / OUTPUT.............................................................................178
GPIO CONTROL .................................................................................................................................................................... 179
GPIO FUNCTION SELECT .................................................................................................................................................... 181
BUTTON DETECT (GPIO INPUT) .......................................................................................................................................... 184
LOGIC ‘1’ AND LOGIC ‘0’ OUTPUT (GPIO OUTPUT)............................................................................................................ 184
INTERRUPT (IRQ) STATUS OUTPUT ................................................................................................................................... 185
OPCLK AND OPCLK_ASYNC CLOCK OUTPUT ................................................................................................................... 185
FREQUENCY LOCKED LOOP (FLL) STATUS OUTPUT ....................................................................................................... 187
FREQUENCY LOCKED LOOP (FLL) CLOCK OUTPUT ......................................................................................................... 187
SPDIF AUDIO OUTPUT ......................................................................................................................................................... 188
PULSE WIDTH MODULATION (PWM) SIGNAL OUTPUT...................................................................................................... 188
HEADPHONE DETECTION STATUS OUTPUT ..................................................................................................................... 188
MICROPHONE / ACCESSORY DETECTION STATUS OUTPUT .......................................................................................... 188
OUTPUT SIGNAL PATH ENABLE/DISABLE STATUS OUTPUT............................................................................................ 189
BOOT DONE STATUS OUTPUT............................................................................................................................................ 189
ASYNCHRONOUS SAMPLE RATE CONVERTER (ASRC) LOCK STATUS OUTPUT........................................................... 190
ASYNCHRONOUS SAMPLE RATE CONVERTER (ASRC) CONFIGURATION ERROR STATUS OUTPUT ......................... 190
ISOCHRONOUS SAMPLE RATE CONVERTER (ISRC) CONFIGURATION ERROR STATUS OUTPUT .............................. 190
OVER-TEMPERATURE, SHORT CIRCUIT PROTECTION, AND SPEAKER SHUTDOWN STATUS OUTPUT ..................... 191
DYNAMIC RANGE CONTROL (DRC) STATUS OUTPUT ...................................................................................................... 191
CONTROL WRITE SEQUENCER STATUS OUTPUT ............................................................................................................ 192
CONTROL INTERFACE ERROR STATUS OUTPUT ............................................................................................................. 192
SYSTEM CLOCKS ENABLE STATUS OUTPUT .................................................................................................................... 192
CLOCKING ERROR STATUS OUTPUT................................................................................................................................. 193
GENERAL PURPOSE SWITCH ............................................................................................................................................. 194
INTERRUPTS ......................................................................................................................195
CLOCKING AND SAMPLE RATES ......................................................................................208
SYSTEM CLOCKING ............................................................................................................................................................. 208
SAMPLE RATE CONTROL .................................................................................................................................................... 208
AUTOMATIC SAMPLE RATE DETECTION............................................................................................................................ 209
SYSCLK AND ASYNCCLK CONTROL................................................................................................................................... 210
MISCELLANEOUS CLOCK CONTROLS................................................................................................................................ 213
BCLK AND LRCLK CONTROL ............................................................................................................................................... 219
CONTROL INTERFACE CLOCKING...................................................................................................................................... 220
FREQUENCY LOCKED LOOP (FLL) ..................................................................................................................................... 220
FREE-RUNNING FLL MODE.................................................................................................................................................. 230
SPREAD SPECTRUM FLL CONTROL................................................................................................................................... 232
GPIO OUTPUTS FROM FLL .................................................................................................................................................. 233
EXAMPLE FLL CALCULATION.............................................................................................................................................. 233
EXAMPLE FLL SETTINGS..................................................................................................................................................... 234
CONTROL INTERFACE.......................................................................................................235
CONTROL WRITE SEQUENCER ........................................................................................239
INITIATING A SEQUENCE..................................................................................................................................................... 239
AUTOMATIC SAMPLE RATE DETECTION SEQUENCES..................................................................................................... 240
JACK DETECT, GPIO, MICDET CLAMP, AND WAKE-UP SEQUENCES .............................................................................. 240
DRC SIGNAL DETECT SEQUENCES.................................................................................................................................... 242
BOOT SEQUENCE ................................................................................................................................................................ 243
SEQUENCER OUTPUTS AND READBACK .......................................................................................................................... 243
PROGRAMMING A SEQUENCE............................................................................................................................................ 244
SEQUENCER MEMORY DEFINITION ................................................................................................................................... 245
CHARGE PUMPS, REGULATORS AND VOLTAGE REFERENCE .....................................247
CHARGE PUMPS AND LDO2 REGULATOR ......................................................................................................................... 247
MICBIAS BIAS (MICBIAS) CONTROL.................................................................................................................................... 247
VOLTAGE REFERENCE CIRCUIT......................................................................................................................................... 248
LDO1 REGULATOR AND DCVDD SUPPLY .......................................................................................................................... 248
w
PD, October 2014, Rev 4.0
5
5 Page 
Production Data
WM8998
The following table identifies the power domain and ground reference associated with each of the input / output pins.
PIN NO
F7
J12
F10
H11
G10
J9
H9
G7
H8
J6
H5
G5
F5
F9
H7
G4
G8
E11
C1
C3
B1
B2
F11
F13
H12
F12
D9
J11
F8
J13
G11
H10
G9
NAME
ADDR
AIF1BCLK
AIF1LRCLK
AIF1RXDAT
AIF1TXDAT
AIF2BCLK
AIF2LRCLK
AIF2RXDAT
AIF2TXDAT
AIF3BCLK
AIF3LRCLK
AIF3RXDAT
AIF3TXDAT
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
IN1ALN/
DMICCLK1
IN1ARN/
DMICDAT1
IN2AN/
DMICCLK2
IN2AP/
DMICDAT2
I¯R¯Q¯
LDOENA
MCLK1
MCLK2
R¯¯E¯S¯E¯T¯
SCLK
SDA
SLIMCLK
SLIMDAT
SPKCLK
SPKDAT
POWER DOMAIN
DBVDD1
DBVDD1
DBVDD1
DBVDD1
DBVDD1
DBVDD2
DBVDD2
DBVDD2
DBVDD2
DBVDD3
DBVDD3
DBVDD3
DBVDD3
DBVDD1
DBVDD2
DBVDD3
DBVDD2
DBVDD1
(when DMICCLK1 function is selected):
MICVDD, MICBIAS1, MICBIAS2 or MICBIAS3
The DMICCLK1 power domain is selectable using IN1_DMIC_SUP
(when DMICDAT1 function is selected):
MICVDD, MICBIAS1, MICBIAS2 or MICBIAS3
The DMICDAT1 power domain is selectable using IN1_DMIC_SUP
(when DMICCLK2 function is selected):
MICVDD, MICBIAS1, MICBIAS2 or MICBIAS3
The DMICCLK2 power domain is selectable using IN2_DMIC_SUP
(when DMICDAT2 function is selected):
MICVDD, MICBIAS1, MICBIAS2 or MICBIAS3
The DMICDAT2 power domain is selectable using IN2_DMIC_SUP
DBVDD1
DBVDD1
DBVDD1
DBVDD1
DBVDD1
DBVDD1
DBVDD1
DBVDD1
DBVDD1
DBVDD1
DBVDD1
GROUND DOMAIN
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
AGND
AGND
AGND
AGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
w
PD, October 2014, Rev 4.0
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet WM8998.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| WM8991 | Mobile Multimedia CODEC | Wolfson Microelectronics |
| WM8993 | Audio Hub CODEC | Wolfson Microelectronics |
| WM8994 | Multi-Channel Audio Hub CODEC | Wolfson Microelectronics |
| WM8995L | Tereo DAC | Wolfson Microelectronics |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |