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PDF WM8962B Data sheet ( Hoja de datos )

Número de pieza WM8962B
Descripción Ultra-Low Power Stereo CODEC
Fabricantes Cirrus Logic 
Logotipo Cirrus Logic Logotipo



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WM8962B
Ultra-Low Power Stereo CODEC with
Audio Enhancement DSP, 2W Stereo Class D Speaker
Drivers and Ground Referenced Headphone Drivers
DESCRIPTION
FEATURES
The WM8962B is a low power, high performance stereo CODEC
designed for portable digital audio applications.
An integrated charge pump provides a ground referenced output
which removes the need for DC-blocking capacitors on the
headphone outputs, and uses the Wolfson ‘Class-W’ amplifier
techniques - incorporating an innovative dual-mode charge
pump architecture - to optimise efficiency and power
consumption during playback. A DC Servo is used to reduce DC
ground offsets. This improves power consumption and
minimises pops and clicks.
Stereo class D speaker drivers provide 2W per channel into 4
BTL loads, with a 5V supply. Low leakage, excellent PSRR and
pop/click suppression mechanisms also allow direct battery
connection to the speaker supply. Flexible speaker boost
settings allow speaker output power to be maximised while
minimising other analogue supply currents.
Control sequences for audio path setup can be pre-loaded and
executed by an integrated sequencer to reduce software driver
development and eliminate pops and clicks via Wolfson’s
SilentSwitch™ technology.
Flexible input configuration: four stereo inputs or eight mono
inputs on Left or Right ADC, with a complete analogue (four
single-ended stereo inputs) and digital microphone interface.
External component requirements are drastically reduced as no
separate microphone, speaker or headphone amplifiers are
required. Advanced on-chip digital signal processing performs
automatic level control for the microphone or line input.
Stereo 24-bit sigma-delta ADCs and DACs are used with low
power over-sampling digital interpolation and decimation filters
and a flexible digital audio interface.
A programmable audio enhancement DSP is included with
multiple preset algorithms. Virtual Surround Sound widens the
stereo speaker audio image, HD Bass enhances low
frequencies, and ReTuneTM flattens the frequency response of
the speaker or microphone path. A configurable DSP includes
additional functions such as 3D widening for recording, a 5-band
parametric EQ and Dynamic Range Controller.
Two high performance PLLs and one Frequency Locked Loop
(FLL) are integrated to enable the user to clock a full audio
system.
The WM8962B operates at analogue supply voltages down to
1.7V, although the digital supplies can operate at voltages down
to 1.62V to save power. The speaker supply can operate at up
to 5.5V. Unused functions can be disabled using software
control to save power.
The WM8962B is supplied in a very small W-CSP package,
ideal for use in hand-held and portable systems.
DAC SNR 98dB (‘A’ weighted), THD -84dB at 48kHz, 1.8V
ADC SNR 94dB (‘A’ weighted), THD -85dB at 48kHz, 1.8V
Stereo Class D Speaker Driver
- 2W per channel into 4BTL speakers
- 2W mono (for improved THD)
- Flexible internal switching clock
Wolfson ‘Class-W’ ultra-low power headphone driver
- Up to 31mW per channel output power at 1% THD+N
into 16at 1.8V
- Ground Referenced
- Low offset (+/- 1.2mV)
- Pop and click suppression
- Control sequencer for pop-minimised power-up/down
- Single register write for default start-up sequence
Microphone Interface
- Single ended four stereo analogue input
- Integrated low noise MICBIAS
- Digital microphone interface
- Programmable ALC / Limiter and Noise Gate
Programmable Audio Enhancement DSP with Presets
- Virtual Surround Sound
- HD Bass
- ReTuneTM
Fixed Audio Processing DSP
- 3D stereo widening
- 5-band Parametric EQ
- Dynamic range controller
- Beep generator
Two integrated PLLs enable clocking of full audio system
Low Power Consumption
- 7.7mW headphone playback
- 8.3mW analogue record mode
Low Supply Voltages
- Analogue 1.7V to 2.0V (Speaker supply up to 5.5V)
- Charge pump 1.7V to 2.0V
- MIC bias amp supply 1.7V to 3.6V
- Digital 1.62V to 2.0V
2-wire I2C and 3- or 4-wire SPI serial control interface
Standard sample rates from 8kHz to 96kHz
W-CSP, 3.6x3.9mm 49-pin
APPLICATIONS
Portable gaming
Mobile multimedia
Voice recorders and Stereo DSC-Camcorder
http://www.cirrus.com
Copyright Cirrus Logic, Inc., 20112015
(All Rights Reserved)
Rev 4.2
FEB ‘15

1 page




WM8962B pdf
WM8962B
REFERENCE VOLTAGES AND BIAS CONTROL...................................................... 138
ANALOGUE REFERENCE AND MASTER BIAS ....................................................................................138
INPUT SIGNAL PATH BIAS CONTROL SETTINGS ...............................................................................139
OUTPUT SIGNAL PATH BIAS CONTROL SETTINGS ...........................................................................140
DIGITAL AUDIO INTERFACE .................................................................................... 141
MASTER AND SLAVE MODE OPERATION ...........................................................................................141
OPERATION WITH TDM.........................................................................................................................142
BCLK FREQUENCY ................................................................................................................................143
AUDIO DATA FORMATS (NORMAL MODE) ..........................................................................................143
AUDIO DATA FORMATS (TDM MODE)..................................................................................................145
DIGITAL AUDIO INTERFACE CONTROL.................................................................. 147
AUDIO INTERFACE TRI-STATE.............................................................................................................148
BCLK AND LRCLK CONTROL................................................................................................................148
COMPANDING ........................................................................................................................................149
LOOPBACK .............................................................................................................................................151
CLOCKING AND SAMPLE RATES ............................................................................ 152
SYSCLK CONTROL ................................................................................................................................153
AUTOMATIC CLOCKING CONFIGURATION .........................................................................................156
DSP, ADC, DAC CLOCK CONTROL.......................................................................................................158
CLASS D, 256K, DC SERVO CLOCK CONTROL...................................................................................159
OPCLK CONTROL ..................................................................................................................................160
TOCLK, DBCLK CONTROL ....................................................................................................................160
BCLK AND LRCLK CONTROL................................................................................................................161
CONTROL INTERFACE CLOCKING ......................................................................................................161
INTERNAL / EXTERNAL CLOCK GENERATION ...................................................... 162
START-UP OPTIONS FOR INTERNAL / EXTERNAL CLOCK GENERATION.......................................163
INTERNAL OSCILLATOR CONTROL .....................................................................................................164
CLKOUT CONTROL................................................................................................................................166
FREQUENCY LOCKED LOOP (FLL) ......................................................................................................168
FREE-RUNNING FLL CLOCK.................................................................................................................172
EXAMPLE FLL CALCULATION...............................................................................................................173
PHASE LOCKED LOOP (PLL) ................................................................................................................174
EXAMPLE PLL CALCULATION ..............................................................................................................178
GENERAL PURPOSE INPUT/OUTPUT (GPIO)......................................................... 179
INTERRUPTS ............................................................................................................ 183
CONTROL INTERFACE............................................................................................. 188
SELECTION OF CONTROL INTERFACE MODE ...................................................................................188
2-WIRE (I2C) CONTROL MODE .............................................................................................................189
3-WIRE (SPI) CONTROL MODE .............................................................................................................192
4-WIRE (SPI) CONTROL MODE .............................................................................................................193
CONTROL WRITE SEQUENCER .............................................................................. 194
INITIATING A SEQUENCE......................................................................................................................194
PROGRAMMING A SEQUENCE ............................................................................................................195
DEFAULT SEQUENCES .........................................................................................................................198
THERMAL SHUTDOWN ............................................................................................ 202
SOFTWARE RESET AND CHIP ID............................................................................ 203
REGISTER MAP ................................................................................................ 204
REGISTER BITS BY ADDRESS ................................................................................ 213
DIGITAL FILTER CHARACTERISTICS ............................................................ 278
DAC FILTER RESPONSES ....................................................................................... 279
ADC FILTER RESPONSES ....................................................................................... 281
ADC HIGH PASS FILTER RESPONSES ................................................................................................282
Rev 4.2
5

5 Page





WM8962B arduino
WM8962B
Test Conditions
MICVDD = DCVDD = DBVDD = CPVDD = AVDD = PLLVDD = 1.8V, SPKVDD1 = SPKVDD2 = 5V.
TA = +25oC, 1kHz signal, fs = 48kHz, PGA gain = 0dB, 24-bit audio data unless otherwise stated.
PARAMETER
SYMBOL TEST CONDITIONS
MIN
Analogue Inputs (IN1L, IN1R) to ADC out via Input PGA and Input Gain Boost
Signal to Noise Ratio
(A-weighted)
Total Harmonic Distortion Plus
Noise (-1dBFS input)
SNR
THD+N
ADC_HP=0
MIXIN_BIAS=100
INPGA_BIAS=100
‘Option 1’ (low power) bias
settings - see Note 2.
Signal to Noise Ratio
(A-weighted)
Total Harmonic Distortion Plus
Noise (-1dBFS input)
SNR
THD+N
ADC_HP=0
MIXIN_BIAS=011
INPGA_BIAS=100
‘Option 2’ bias settings -
see Note 2.
Signal to Noise Ratio
(A-weighted)
Total Harmonic Distortion Plus
Noise (-1dBFS input)
SNR
THD+N
ADC_HP=0
MIXIN_BIAS=000
INPGA_BIAS=100
‘Option 3’ bias settings -
see Note 2.
81
Signal to Noise Ratio
(A-weighted)
Total Harmonic Distortion Plus
Noise (-1dBFS input)
SNR
THD+N
ADC_HP=1
MIXIN_BIAS=000
INPGA_BIAS=000
‘Option 4’ (high performance)
bias settings - see Note 2.
ADC Channel Separation
1kHz
10kHz
PSRR (AVDD)
100mV(peak-peak) 1kHz
100mV(peak-peak) 20kHz
Channel Matching
1kHz signal
TYP
91
-70
91
-75
91
-82
93
-82
95
97
60
40
+/-0.5
MAX
UNIT
dB
dB
dB
dB
dB
-72 dB
dB
dB
dB
dB
dB
Rev 4.2
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11 Page







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