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PDF MAAP-015036 Data sheet ( Hoja de datos )

Número de pieza MAAP-015036
Descripción Power Amplifier
Fabricantes MA-COM 
Logotipo MA-COM Logotipo



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MAAP-015036
Power Amplifier, 15 W
8.5 - 10.5 GHz
Features
15 W Power Amplifier
42 dBm Saturated Pulsed Output Power
17 dB Large Signal Gain
PSAT >40% Power Added Efficiency
Dual Sided Bias Architecture
On Chip Bias Circuit
100% On-Wafer DC, RF and Output Power
Testing
100% Visual Inspection to MIL-STD-883 Method
2010
Description
The MAAP-015036 is a two stage GaAs MMIC
power amplifier operating from 8.5 - 10.5 GHz, with
a saturated pulsed output power of 42 dBm and a
large signal gain of 18 dB.
This power amplifier uses GaAs pHEMT device
technology and is based upon optical gate
lithography to ensure high repeatability and
uniformity. The chip has surface passivation for
protection and backside via holes and gold
metallisation to allow a conductive epoxy die attach
process.
This device is well suited for communications, Point
to Point radio and radar applications.
Ordering Information
MAAP-015036-DIE
MAAP-015036-DIEEV1
MAAP-015036-DIEEV2
1. Die quantity varies.
Die in Gel Pack1
Sample Board
Direct Gate Bias
Sample Board
On-Chip Gate Bias
Functional Schematic
Rev. V1
Pin Configuration2
1 VG1 15 VD2
2 GND 16 GND
3 VSS1 17 GND
4 V1_5 18 VD1
5
GND
19
VG2
6 VSS2 20 GND
7 V2_5 21 V2_5
8 GND 22 VSS2
9 VG2 23 GND
10 VD1 24 V1_5
11 GND 25 VSS1
12 GND 26 GND
13 VD2 27
14 RFOUT 28
VG1
RFIN
2. Backside metal is RF, DC and thermal ground.
* Restrictions on Hazardous Substances, European Union Directive 2011/65/EU.
1
M/A-COM Technology Solutions Inc. (MACOM) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice.
Visit www.macom.com for additional data sheets and product information.
For further information and support please visit:
https://www.macom.com/support

1 page




MAAP-015036 pdf
MAAP-015036
Power Amplifier, 15 W
8.5 - 10.5 GHz
Rev. V1
Pulsed Performance Curves over Gate Voltage: PIN = 25 dBm, Duty Cycle = 5%, Pulse = 5 µs
Gain vs. Frequency
Output Power vs. Frequency
Drain Current vs. Frequency
PAE vs. Frequency
5
M/A-COM Technology Solutions Inc. (MACOM) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice.
Visit www.macom.com for additional data sheets and product information.
For further information and support please visit:
https://www.macom.com/support

5 Page





MAAP-015036 arduino
MAAP-015036
Power Amplifier, 15 W
8.5 - 10.5 GHz
Applications Section
Rev. V1
Application Notes
Note 1 - Biasing
The gate bias is applied in one of the following:
1. Direct Gate Bias:- VG1 & VG2 provide the direct
gate bias input to the 2 MMIC stages. This
method of biasing allows the user to control the
total drain current without the scaling factor
provided by the bias circuit . It is recommended
that the gate voltage is supplied by both sides
of the die. Biasing from one side is optional.
Optimum performance can be achieved with a
-0.9 V operation.
2. Bias Circuit Biasing:- Applying -5 V to VSS1 &
VSS2, will typically draw 4.5 A with no further
adjustment necessary. Wafer lot variation may
result in some devices experiencing higher or
lower drain currents than the typical 4.5 A. It is
recommended that the bias circuits on both
sides of the PA are used. Biasing from one
side is optional.
Note 2 - Bias Sequence
When switching on the PA, In each case, the gate
bias must be applied before the drain voltage is
applied. The drain voltage VD1 & VD2 should be
biased from the top and bottom sides of the die.
Note 3 - Decoupling Circuits
Each bias pad, VG, VSS & VD must have a
decoupling capacitor of 120 pF as close to the
device as possible, as is shown in the bonding
diagrams. Symmetrical decoupling circuits must be
maintained on both sides of the die for bias circuit
or direct gate bias operation.
Under pulsed operation a large capacitance on the
drain will cause a “ringing” effect on the supply
voltage. This potentially produces a high voltage at
the PA terminals. A recommended decoupling
circuit is provided where shunt decoupling
capacitors are connected in series with a resistor to
minimize this effect.
Note 4 - Pulse Operation
The performance of the MAAP-015036 is
characterized under pulsed conditions with a duty
cycle of 5% consisting of a pulse width of 5 µS
applied to the drain. Under pulsed conditions the
gate is constantly biased using either the on chip
bias circuit or using a gate voltage directly applied
to the PA. It is recommended that the die is mount-
ed with an adequate thermal solution.
Note 5 - Input / Output Transitions
The PA performance must be achieved in a 50 Ω
impedance environment on the RF input and
output. To maintain performance three bond wires
are recommended on the output of the PA each
with a maximum length of less than 600 µm. Long-
er bond wire lengths can be used providing bond
pad compensation, in the form of a stub, is used on
the application board.
11
M/A-COM Technology Solutions Inc. (MACOM) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice.
Visit www.macom.com for additional data sheets and product information.
For further information and support please visit:
https://www.macom.com/support

11 Page







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