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PDF CS4205-KQ Data sheet ( Hoja de datos )

Número de pieza CS4205-KQ
Descripción CrystalClear Audio Codec 97
Fabricantes Cirrus Logic 
Logotipo Cirrus Logic Logotipo



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No Preview Available ! CS4205-KQ Hoja de datos, Descripción, Manual

CS4205
CrystalClear® Audio Codec ’97 for Portable Computing
Features
! Integrated Asynchronous I2S Input Port
(ZV Port)
! Integrated High-Performance Microphone
Pre-Amplifier
! Integrated Digital Effects Processing for Bass
and Treble Response
! Digital Docking Including an I2S Output, 3
Synchronous I2S Inputs
! Performance Oriented Digital Mixer
! SRS© 3D Stereo Enhancement
! On-chip PLL for use with External Clock
Sources
! Dedicated Microphone Analog-to-Digital
Converter
! Sample Rate Converters
! S/PDIF Digital Audio Output
! AC ’97 2.1 Compliant
! PC Beep Bypass
! 20-bit Stereo Digital-to-Analog Converters
! 18-bit Stereo Analog-to-Digital Converters
! Three Analog Line-level Stereo Inputs for
LINE IN, VIDEO, and AUX
! High Quality Pseudo-Differential CD Input
! Extensive Power Management Support
! Meets or Exceeds the Microsoft® PC 99 and
PC 2001 Audio Performance Requirements
Description
The CS4205 is an AC ’97 2.1 compliant stereo audio co-
dec designed for PC multimedia systems. It uses
industry leading CrystalClear® delta-sigma and mixed
signal technology. The CS405 is the first Cirrus AC ’97
audio codec to feature digital centric mixing and digital
effects. This advanced technology and these features
are designed to help enable the design of PC 99 and
PC 2001 compliant high-quality audio systems for desk-
top, portable, and entertainment PCs.
Coupling the CS4205 with a PCI audio accelerator or
core logic supporting the AC ’97 interface implements a
cost effective, superior quality audio solution. The
CS4205 surpasses PC 99, PC 2001, and AC ’97 2.1 au-
dio quality standards.
ORDERING INFO
CS4205-KQZ, Lead Free 48-pin TQFP 9x9x1.4 mm
SYNC
BIT_CLK
SDATA_OUT
SDATA_IN
RESET#
ID0#
ID1#
GPIO0/LRCLK
GPIO1/SDOUT
EAPD/SCLK
SPDO/SDO2
GPIO[2:4]/SDI[1:3]
ZSCLK,ZSDATA,ZLRCLK
AC-LINK AND AC '97
REGISTERS
TEST
PWR
MGT
AC-
LINK
AC
'97
REG
SIGNAL
PROCESSING
ENGINE
ANALOG INPUT MUX
AND OUTPUT MIXER
SRC PCM_DATA
SRC MIC_PCM_DATA
GAIN / MUTE CONTROLS
MIXER / MUX SELECTS
18 bit
ADC
(2ch)
18 bit
ADC
(1ch)
INPUT
MUX
INPUT
MIXER
Σ
GPIO
S/PDIF
SERIAL DATA PORT
ZV PORT
OUTPUT
MIXER
Σ20 bit
SRC PCM_DATA DAC
(2ch)
LINE
CD
AUX
VIDEO
MIC1
MIC2
PHONE
PC_BEEP
LINE_OUT
MONO_OUT
Preliminary Product Information
http://www.cirrus.com
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Copyright © Cirrus Logic, Inc. 2005
(All Rights Reserved)
JULY '05
DS489PP4
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CS4205-KQ pdf
CS4205
Figure 25. Line Input (Replicate for Video and AUX) .................................................................... 64
Figure 26. Differential 2 VRMS CD Input ...................................................................................... 64
Figure 27. Differential 1 VRMS CD Input ...................................................................................... 64
Figure 28. Microphone Input ......................................................................................................... 65
Figure 29. PC_BEEP Input ........................................................................................................... 65
Figure 30. Modem Connection...................................................................................................... 65
Figure 31. Stereo Output............................................................................................................... 66
Figure 32. +5V Analog Voltage Regulator .................................................................................... 66
Figure 33. Conceptual Layout for the CS4205 when in XTAL or OSC Clocking Modes............... 69
Figure 34. Pin Locations for the CS4205 ...................................................................................... 70
Figure 35. CS4205 Reference Design .......................................................................................... 79
DS489PP4
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CS4205-KQ arduino
BIT_CLK
RESET#
Vdd
Trst_low
Tvdd2rst#
Trst2clk
Figure 1. Power Up Timing
BIT_CLK
SYNC
CODEC_READY
Tsync2crd
Figure 2. Codec Ready from Start-up or Fault Condition
CS4205
BIT_CLK
Torise
SYNC
Tirise
Tclk_high Tclk_low
Tclk_period
Tifall
Tsync_high Tifall
Tsync_period
Tsync_low
Figure 3. Clocks
DS489PP4
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