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PDF UT28F256LV Data sheet ( Hoja de datos )
| Número de pieza | UT28F256LV | |
| Descripción | Radiation-Hardened 32K x 8 PROM | |
| Fabricantes | Aeroflex Circuit Technology | |
| Logotipo |  |
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Standard Products
UT28F256LV Radiation-Hardened 32K x 8 PROM
Data Sheet
December, 2002
FEATURES
q Programmable, read-only, asynchronous, radiation-
hardened, 32K x 8 memory
- Supported by industry standard programmer
q 65ns maximum address access time (-55 oC to
+125 oC)
q Three-state data bus
q Low operating and standby current
- Operating: 50.0mA maximum @15.4MHz
• Derating: 1.5mA/MHz
- Standby: 1.0mA maximum (post-rad)
q Radiation-hardened process and design; total dose
irradiation testing to MIL-STD-883, Method 1019
- Total dose: 1E6 rad(Si)
- LETTH(0.25) ~ 100 MeV-cm2/mg
- SEL Immune >128 MeV-cm2/mg
- Saturated Cross Section cm2 per bit, 1.0E-11
- 1.2E-8 errors/device-day, Adams 90% geosynchronous
heavy ion
- Memory cell LET threshold: >128 MeV-cm2/mg
q QML Q & V compliant part
- AC and DC testing at factory
q Packaging options:
- 28-lead 50-mil center flatpack (0.490 x 0.74)
- 28-lead 100-mil center DIP (0.600 x 1.4) - contact factory
q VDD: 3.0Vto 3.6V
q Standard Microcircuit Drawing 5962-01517
PRODUCT DESCRIPTION
The UT28F256LV amorphous silicon anti-fuse PROM is a high
performance, asynchronous, radiation-hardened, 32K x 8
programmable memory device. The UT28F256LV PROM
features fully asychronous operation requiring no external clocks
or timing strobes. An advanced radiation-hardened twin-well
CMOS process technology is used to implement the
UT28F256LV. The combination of radiation-hardness, fast
access time, and low power consumption make the UT28F256LV
ideal for high speed systems designed for operation in radiation
environments.
A(14:0)
DECODER
MEMORY
ARRAY
CE
CONTROL
PE LOGIC
OE
SENSE AMPLIFIER
PROGRAMMING
Figure 1. PROM Block Diagram
DQ(7:0)
1
1 page  
READ CYCLE
A combination of PE greater than VIH(min), and CE less than
VIL(max) defines a read cycle. Read access time is measured
from the latter of device enable, output enable, or valid address
to valid data output.
An address access read is initiated by a change in address inputs
while the chip is enabled withOE asserted and PE deasserted.
Valid data appears on data output, DQ(7:0), after the specified
tAVQV is satisfied. Outputs remain active throughout the entire
cycle. As long as device enable and output enable are active, the
address inputs may change at a rate equal to the minimum read
cycle time.
The chip enable-controlled access is initiated byCE going active
while OE remains asserted, PE remains deasserted, and the
addresses remain stable for the entire cycle. After the specified
tELQV is satisfied, the eight-bit word addressed by A(14:0)
appears at the data outputs DQ(7:0).
Output enable-controlled access is initiated by OE going active
while CE is asserted, PE is deasserted, and the addresses are
stable. Read access time is tGLQV unless tAVQV or tELQV have
not been satisfied.
AC CHARACTERISTICS READ CYCLE (Post-Radiation)*
(VDD = 3.0V to 3.6V; -55°C < TC < +125°C)
SYMBOL
PARAMETER
tAVAV 1
tAVQV
tAXQX 2
tGLQX2
tGLQV
tGHQZ
tELQX2
tELQV
tEHQZ
Read cycle time
Read access time
Output hold time
OE-controlled output enable time
OE-controlled access time
OE-controlled output three-state time
CE-controlled output enable time
CE-controlled access time
CE-controlled output three-state time
28F256LV-65
MIN
MAX
65
UNIT
ns
65 ns
0 ns
0 ns
35 ns
35 ns
0 ns
65 ns
35 ns
Notes:
* Post-radiation performance guaranteed at 25 °C per MIL-STD-883 Method 1019 at 1E6 rads(Si).
1. Functional test.
2. Three-state is defined as a 400mV change from steady-state output voltage.
5
5 Page 
Notes
11
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| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet UT28F256LV.PDF ] | |
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